I have a Makefile which looks like below. I use ifeq to add variables to compiler flags.
ABC=1
XYZ=1
ifeq ($(ABC),1)
CFLAGS+= -DABC
endif
ifeq ($(XYZ),1)
CFLAGS+= -DXYZ
endif
...
Is there a cleaner way to add all variables to CFLAGS instead of using ifeq for all?
Is there a cleaner way to add all variables to CFLAGS instead of using ifeq for all?
You can use computed variable names to avoid those verbose ifeq blocks:
ABC=1
XYZ=1
cflags.abc.1 := -DABC
cflags.xyz.1 := -DXYZ
CFLAGS += cflags.abc.${ABC} cflags.xyz.${XYZ}
It uses the fact that unset variables expand to empty strings in GNU make.
Related
Is there a way to convince make to accept a user-supplied macro and then expand on it? One simple example of what I mean is that I would like the user to be able to issue:
> make CFLAGS='-g'
and then somewhere in Makefile would be a line like:
CFLAGS := $(CFLAGS) -O2
so that, altogether CFLAGS would evaluate to -g -O2. AFAICT, if the user issues that command, make takes CFLAGS as -g and won't touch it further. Of course, I could have the user issue something like
> make CFIN='-g'
and then in the Makefile put
CFLAGS := $(CFIN) -O2
but that just seems a bit "clunky" to me.
Do this:
CFLAGS :=
override CFLAGS := $(CFLAGS) -O2
The first assignment prevents the contents of CFLAGS environment variable from being imported as the Make variable with the same name. If you want this behavior, remove the first line.
I recently discovered that
setting a Target-specific Variable
using a conditional assignment (?=)
has the effect of unexporting the global variable using the same name.
For example:
target: CFLAGS ?= -O2
If this statement is anywhere in the Makefile, it has the same impact as unexport CFLAGS for the global variable.
It means that the CFLAGS passed as environment variable to the Makefile will not be passed as environment variable to any sub-makefile, as if it was never set.
Could it be a make bug ?
I couldn't find any mention of this side effect in the documentation.
Example : root Makefile
target:
$(MAKE) -C $(DIR) target
disruptor: CFLAGS ?= -O1
disruptor:
#echo CFLAGS = $(CFLAGS)
and then into $DIR/Makefile:
target:
#echo target CFLAGS = $(CFLAGS)
Now :
make will display target CFLAGS =
make CFLAGS=-Os will display target CFLAGS = -Os
but CFLAGS=-Os make will display target CFLAGS =
after commenting the first disruptor line (CFLAGS ?= -O1), then CFLAGS=-Os make will display target CFLAGS = -Os as expected.
Other mitigations that work :
adding export CFLAGS after the first disruptor line
replacing the ?= assignment by =, := or +=. None of them produce the "implicit unexport" side effect (of course, it also changes the assignment meaning, this is just for test).
I haven't tested with other variable names yet, but I presume it's not specific to CFLAGS.
I reproduce your observed behavior with GNU make 4.0. I concur with your characterization that the effect seems to be as if the variable in question had been unexported, and I confirm that the same effect is observed with other variable names, including names that are without any special significance to make.
This effect is undocumented as far as I can tell, and unexpected. It seems to conflict with the manual, in that the manual describes target-specific variable values as causing a separate instance of the affected variable to be created, so as to avoid affecting the global one, yet we do see the global one being affected.
Could it be a make bug ?
It indeed does look like a bug to me. Evidently to other people, too, as it appears that the issue has already been reported.
I was a little confused with the responses to Quick way to override -Werror flag?
So I ask my specific question here.
I have multiple Makefiles working together and CFLAGS has been set along the way to (-Werror -Wall .. and many others)
But in one of the Makefiles, I wish that the errors not be treated as warnings and so I would like to remove -Werror flag.
What would be the best way to achieve this, so that only for this Makefile, -Werror flag is removed and for the others normal execution takes place?
Thanks,
Sunny
The right way to do this is with the filter-out function.
Put
CFLAGS := $(filter-out -Werror,$(CFLAGS))
in the Makefile where you want to override this, and the -Werror part of CFLAGS will be removed in that Makefile.
You can even use this to override flags for a single target by using target-specific variable values:
CFLAGS = -Werror
all: foo bar
foo:
echo cc $(CFLAGS) -o $#
bar: CFLAGS := $(filter-out -Werror,$(CFLAGS))
bar:
echo cc $(CFLAGS) -o $#
foo will be built with the default CFLAGS containing -Werror, but bar will be built without.
This is a general-purpose solution that works for all arguments to all programs, rather than requiring each program to supply a --no-foo for every --foo option.
Because it can’t be done from Make command-line, it doesn’t directly answer the question you linked to. But overriding Make variables from the command-line to force stuff to build is a pretty good way to make your unbuildable code even less maintainable!
Simpler way
It looks like you can invoke
gcc -c ... -Werror ... -Wno-error ...
without having GCC complain (GCC 4.7.1). So, you can add -Wno-error to the CFLAGS set up elsewhere in the one makefile where you need it. If you're using GNU make, in the one makefile, you can add:
CFLAGS += -Wno-error
possibly for just the single target that needs it.
Harder way
Otherwise, you need a system for building CFLAGS from components. What I have in the makefile I use for testing answers to questions on SO is:
WFLAG1 = -Wall
WFLAG2 = -Wextra
WFLAG3 = -Wmissing-prototypes
WFLAG4 = -Wstrict-prototypes
WFLAG5 = -Wold-style-definition
WFLAG6 =
WFLAGS = ${WFLAG1} ${WFLAG2} ${WFLAG3} ${WFLAG4} ${WFLAG5} ${WFLAG6}
SFLAGS = -std=c99
GFLAGS = -g
OFLAGS = -O3
UFLAGS =
IFLAG1 = -I${HOME}/inc
IFLAGS = # ${IFLAG1}
CFLAGS = ${OFLAGS} ${GFLAGS} ${IFLAGS} ${SFLAGS} ${WFLAGS} ${UFLAGS}
The main point is that each flag is independently adjustable; I can control the warning flags by setting any of ${WFLAG1} to ${WFLAG6}, or by setting ${WFLAGS} wholesale on the command line, or (indeed) by setting ${CFLAGS}. But because each is individually adjustable, and can tune the warnings relatively easily (the main hassle being determining which WFLAGn needs clobbering).
The UFLAGS is 'user flags' and is only set on the command line; I can add more flags to my command line by setting it.
This way is 'harder' because it requires you to modify the central part of your makefile system where you set CFLAGS. It is also less likely to be understood by your colleagues at first sight.
You can see an example of variable overriding in Git Makefile with CFLAGS which now can be tweaked when invoking Make while using DEVELOPER=YesPlease, with Git 2.22 (Q2 2019)
DEVELOPER (in Git Makefile) is a variable to group more compiler warning.
See commit 6d5d4b4, commit 71a7894, commit 8fb2a23, commit 65260a4, commit 9559f8f, commit 4f14a8c (22 Feb 2019) by Ævar Arnfjörð Bjarmason (avar).
(Merged by Junio C Hamano -- gitster -- in commit 3cef676, 20 Mar 2019)
Makefile: allow for combining DEVELOPER=1 and CFLAGS="..."
Ever since the DEVELOPER=1 facility introduced there's been no way to have custom CFLAGS (e.g. CFLAGS="-O0 -g -ggdb3") while still benefiting from the set of warnings and assertions DEVELOPER=1 enables.
This is because the semantics of variables in the Makefile are such
that the user setting CFLAGS overrides anything we set, including what
we're doing in config.mak.dev.
So let's introduce a "DEVELOPER_CFLAGS" variable in config.mak.dev and
add it to ALL_CFLAGS. Before this the ALL_CFLAGS variable
would (basically, there's some nuance we won't go into) be set to:
$(CPPFLAGS) [$(CFLAGS) *or* $(CFLAGS) in config.mak.dev] $(BASIC_CFLAGS) $(EXTRA_CPPFLAGS)
But will now be:
$(DEVELOPER_CFLAGS) $(CPPFLAGS) $(CFLAGS) $(BASIC_CFLAGS) $(EXTRA_CPPFLAGS)
The reason for putting DEVELOPER_CFLAGS first is to allow for
selectively overriding something DEVELOPER=1 brings in.
On both GCC and Clang later settings override earlier ones.
E.g. "-Wextra -Wno-extra" will enable no "extra" warnings, but not if those two
arguments are reversed.
Examples of things that weren't possible before, but are now:
# Use -O0 instead of -O2 for less painful debuggng
DEVELOPER=1 CFLAGS="-O0 -g"
# DEVELOPER=1 plus -Wextra, but disable some of the warnings
DEVELOPER=1 DEVOPTS="no-error extra-all" CFLAGS="-O0 -g -Wno-unused-parameter"
The reason for the patches leading up to this one re-arranged the
various *FLAGS assignments and includes is just for readability.
The Makefile supports assignments out of order, e.g.:
$ cat Makefile
X = $(A) $(B) $(C)
A = A
B = B
include c.mak
all:
#echo $(X)
$ cat c.mak
C=C
$ make
A B C
I'm trying to do an ifeq inside of a define within a Makefile, but I seem to be running into some errors, and I'm wondering if I'm missing something. I have the following Makefile:
$(info ---- start ----)
ifeq ("X","Y")
$(info DOES not appear_1)
endif
define TESTDEF
ifeq ("X","Y")
$(info SHOULD not appear)
# $(error DEFINITELY SHOULD not error...)
endif
endef
$(eval $(call TESTDEF, 1,2,3))
I'm getting the following error:
---- start ----
SHOULD not appear
Makefile:14: *** DEFINITELY SHOULD not error.... Stop.
Is there some trick that I'm missing? Is it possible to do ifeq's inside define? (note: this happens on both my native GNU 3.81 make, and on my mips uclibc cross-compiler)
When you call this function, Make evaluates the definition, using whatever parameters you provide (irrelevant in this case). So if the definition includes something like $(info ...) or $(error ...), even in a comment, Make will evaluate it and you'll see the result (see documentation; I've tested it in GNUMake 3.81).
To get the behavior you want, add a couple of dollar signs:
define TESTDEF
ifeq ("X","Y")
$$(info SHALL not appear)
# $$(info DEFINITELY SHALL not error...)
endif
endef
$(eval $(call TESTDEF))
I'm experimenting with an updated build system at work; currently, I'm trying to find a good way to set compiler & flags depending on the target platform.
What I would like to do is something like
switch $(PLATFORM)_$(BUILD_TYPE)
case "Linux_x86_release"
CFLAGS = -O3
case "Linux_x86_debug"
CFLAGS = -O0 -g
case "ARM_release"
CC = armcc
AR = armlink
CFLAGS = -O2 -fx
...
which is not supported by GNU Make. Now, my first thought was to just do
-include $(PLATFORM)_$(BUILD_TYPE)
which is a pretty decent solution, however, it makes it hard to get an overview of what differs between files, not to mention that I'm looking forward to writing & maintaining a good 60-80 files, each containing a set of variable definitions.
Does anyone happen to know a better way to accomplish this? I.e. setting a set of flags and other options based on another variable?
How about:
CFLAGS_Linux_x86_release = -O3
CFLAGS_Linux_x86_debug = -O0 -g
CFLAGS = ${CFLAGS_${PLATFORM}_${BUILD}}
Configuring such parameters would be the task of a configure script.
That being said, you can look into the syntax for conditionals and conditional functions. For example, you could try the following:
ifeq ($(PLATFORM)_$(BUILD_TYPE),Linux_x86_release)
CFLAGS = -O3
endif
ifeq ($(PLATFORM)_$(BUILD_TYPE),Linux_x86_debug)
CFLAGS = -O0 -g
endif
The Makefile used by git is a good example of a Makefile which does non-trivial configuration tasks in the Makefile itself (such as switching on the host type). It's actually quite readable and reasonably simple to use.
Switching to a system which does it for you (automake/autoconf) may be simpler...