Files to enable build of out-of-tree kernel modules - linux-kernel

I need to prepare an apt-package for stuff to enable building kernel modules for a custom Linux. I have cross-built on a different machine the kernel headers and modules using headers_install and modules_install make-targets. After copying the generated directories I'm still not able to build kernel modules on the target machine since /lib/modules/$(shell uname -r)/build is missing.
Here is my question. What are the minimal dependencies I need to include to my package in order to enable module builds (alongside with the generated kernel headers and modules mentioned above)?
Thanks in advance.

After some experimenting I've got to a working solution:
#!/bin/bash
ARCH=arm
SRC_DIR=$1
MOD_DIR=$2
BUILD_DIR=$MOD_DIR/build
set -ex
cd $SRC_DIR
make modules_install INSTALL_HDR_PATH=$MOD_DIR
rm $MOD_DIR/{build,source}
mkdir $BUILD_DIR
cp $SRC_DIR/{.config,Makefile,System.map,Module.symvers} $BUILD_DIR
mkdir -p $BUILD_DIR/arch/$ARCH
cp $SRC_DIR/arch/$ARCH/Makefile $BUILD_DIR/arch/$ARCH/
cp -r $SRC_DIR/scripts $BUILD_DIR/
# Build a headers tree manually, because
# `make headers_install` doesn't put everything needed.
cp -r $SRC_DIR/include $BUILD_DIR/
cp -r $SRC_DIR/arch/$ARCH/include/* $BUILD_DIR/include/
cp -r $SRC_DIR/include/generated/* $BUILD_DIR/include/
cp -r $SRC_DIR/arch/$ARCH/include/generated/* $BUILD_DIR/include/
cp $SRC_DIR/include/linux/kconfig.h $BUILD_DIR/include/linux/
This script is fed with a path to a kernel source tree after the latter was built natively (not cross-platform).

Related

how to enable host compilation but not cross compilation on yocto on certain files

I am trying to build gutenprint 5.2.14 for arm platform using yocto project "devtool". During the compile process, I am getting this error for the file "lt-extract-strings" saying cannot binary execute file: Exec format error
Upon looking at the file, it a 32-bit arm-executable.
OpenWRT says to implement this when doing cross-compilation.
define Build/Compile
# Replace the cross-compiled "extract-string" by a shell-script that
# runs the host's own compiled version (gutenprint needs to run this)
(cd $(PKG_BUILD_DIR) && $(MAKE) -C src/xml extract-strings && \
$(RM) src/xml/extract-strings && \
echo '#!/bin/sh' > src/xml/extract-strings && \
echo 'exec $(HOST_BUILD_DIR)/src/xml/extract-strings "$$$$#" ' \
>> src/xml/extract-strings && chmod +x src/xml/extract-strings && cp src/xml/extract-strings /tmp/)
$(call Build/Compile/Default)
endef
the link to the file is here
I tried looking for sources on how to implement this fix above in a yocto recipe but I had no luck finding it. Can someone help me solve this issue ?
Thanks in advance

Make: Can we have directories as a target in GNUmakefile

I am working on GNUmake to create symlink to specific file by parsing whole directory which has a folder which needs to be linked.
Here is my makefile snippet.
TGT_LINK = /lan/test/workspace/build/tools
all_target: release_buid complete_test $(TGT_LINK)
$(TGT_LINK):
if [ ! -d $# ]; then mkdir -p $#; fi
cd $#; \
tar_ln=`\ls -d synopsystcl* | sed 's/synopsys//'`; \
sour_dir=`\ls -d synopsystcl*`; \
if ! [ -e $tar_ln ]; then \
ln -s $sour_dir $tar_ln; \
fi
Directory : /lan/test/workspace/build/tools Contains following content in it
polaris.so link.a dynamic.so kbuild.so README.txt license.txt synopsystcl5.5 build.json
Here i am trying to create symlink with name tcl5.5 pointing to synopsystcl5.5 with my above target $(TGT_LINK) code.
tcl5.5 -> synopsystcl5.5
After successful completion of two targets : release_buid complete_test , build is not proceeding to go for next target $(TGT_LINK) to create symlink. Could you please help whats wrong in code?
I would let make itself to check and recreate symlink as needed, i.e.:
TGT_LINK = /lan/test/workspace/build/tools
all_target: release_buid complete_test symlink
.PHONY: symlink
symlink: $(patsubst $(TGT_LINK)/tcl%, $(TGT_LINK)/synopsystcl%, $(wildcard $(TGT_LINK)/tcl*))
$(TGT_LINK)/synopsystcl%: $(TGT_LINK)/tcl%
set -e; \
cd $(#D); \
rm -f $(#F); \
ln -s $(<F) $(#F)
I would also consider reordering targets if there are dependencies indeed. One should never assume that dependency list is processed left to right; it will also lead to errors when parallel build (-j) is involved. If you have dependencies that something should happen before something else, it should be explicitly stated, e.g.:
all_target: symlink
symlink: complete_test
complete_test: release_buid

How to execute a make target on file change automatically?

How do I write a make target that will watch for any file changes in specific folders and execute some other make target to compile files? I am looking for a way that can do this with minimal dependency on tools in addition to make itself to keep things simple.
For the watching you can use fswatch. (There's also a go version of this program which may be easier to install: fswatch) For example:
fswatch -ext cpp,c,h make -f Makefile
Anytime you change a cpp, c or h file it will run make again.
Make can be a bit slow for this, so I tend to use ninja instead, but that really depends on the size of your project.
Another option is tup, which has watching built-in:
tup monitor
But, sadly, only for linux.
You can use entr and adjust your Makefile similar to this one
.DEFAULT_GOAL := run
SHELL := /bin/bash
run:
clear && \
cp one.txt two.txt && \
rm -f _* *.l2m *.o2m && \
Ganlib < testgan2.x2m
watch:
while sleep 1 ; do find . -name '*.x2m' -o -name '*.c2m' \
| entr -d make -f ./Makefile ; done
.PHONY: run watch
followed by
$ make watch

Why does following makefile rebuilt target "build" everytime

I have the following code to untar all the files in a directory and move it to build directory. If I call make multiple times, it tries to execute "build" target everytime even if build directory already exists. Has anyone comes across this?
I found this question but it is not the same.
Makefile always running target
OS: Ubuntu 12.04
Program: GNU Make 3.81
build: mkBuildDir untar
chmod 700 build
.PHONY: mkBuildDir untar
mkBuildDir:
mkdir build
untar: *.tar.gz
for prefix in *.tar.gz; do \
tar xvf $$prefix --directory=build; \
done
clean:
rm -Rf build
This is pretty much the same as the question you've linked. You never create a file called mkBuildDir, so it's always out-of-date, so build is always out of date.
Your mkBuildDir target isn't doing anything useful (though I presume this is a cut-down makefile). If instead you did
# it'd be better to list the TARFILES explicitly, though this will probably work
TARFILES=`ls *.tar.gz`
all: build untar
build: $(TARFILES)
test -d build || mkdir build
chmod 700 build
for prefix in $(TARFILES); do \
tar xvf $$prefix --directory=build; \
done
clean:
rm -Rf build
that would probably accomplish what you're looking for.
Having too many phony targets in a Makefile is usually a makefile 'code smell'. They are rarely the best/idiomatic way of doing things.

Make install causes recompiles

I am writing a master makefile to compile and install multiple autoconf based libraries, which depend on each other. All works well for the first go. The issue is: if I am working on one of these libraries individually and do "make && make install" header files in the prefix folder are overwritten (even if they are untouched). This causes all dependent libraries to compile from scratch.
Is there a way to avoid the unnecessary recompiles without hacking into the makefiles?
Maybe the solution is a little late, but
./configure INSTALL="install -p"
fixes the recompilation problem. This flag makes GNU install set the timestamps of the installed files to the timestamps of the built files.
You could use sentinel files that exist only to establish your dependency graph. For eg.
prefix := /usr/local
.PHONY: all
all: libx-built
libx-built \
: libx.tar.gz \
; tar xzvf $# \
&& cd libx \
&& ./configure --prefix=$(prefix) \
&& make && make install \
&& touch $#
Then, you'd make a dependent liby build only when libx-built is new.
liby-built \
: liby.tar.gz libx-built \
; ...

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