Hi is there any way to add `ifdef in .f files. I have a .f file which includes hierarchial compilation.
`ifdef ASIC
rtl/a.v
`else
rtl/b.v
endif
this is my intention if ASIC is passed as define a.v needs to compile. else b.v. Does the above code works without adding any extra things?
I'm not aware of any tool that does this on the command line. Either create the .f file dynamically as part of your build process, or use a Verilog file to do this instead.
`ifdef ASIC
`include "rtl/a.v"
`else
`include "rtl/b.v"
`endif
Related
I would like to understand how the preprocessor inlines includes into the code in Fortran. With C, it's pretty simple:
Test.c:
#include <stdio.h>
int main(void) {
return 0;
}
Then I compile using:
gcc -E test.c
Then it displays the content generated by the C preprocessor, as expected.
Now assume I have this Fortran code:
Test.f:
program test
include "mpif.h"
call mpi_init
call mpi_finalize
end
Then I run:
gfortran -E -cpp test.f // For some reason I need -cpp when using -E in Fortran
But I won't have the expected result, which is the generated include embedded into the code.
Instead, I have this:
# 1 "test.f"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "test.f"
program test
include 'mpif.h'
call mpi_init
call mpi_finalize
end
What am I doing wrong here?
Fortran has its own include directive which must not be confused with the preprocessor directive #include. As far as I understand it, the included code is not embedded into the master file, but the compiler instead continues to compile from the include file, and returns to the master file at the end of that file. From here:
The INCLUDE statement directs the compiler to stop reading statements
from the current file and read statements in an included file or text
module.
Also, included files are not preprocessed further, while #included ones are.
Note, that there is also a naming convention that enables the preprocessor only on files with capital suffixes *.F and *.F90. If you want to preprocess *.f or *.f90 files, you need to specify that in a compile option, e.g. -cpp for gfortran, and -fpp for ifort.
I would like to know how to add a prerequisite to a rule with an empty recipe in GNU make. Here is a short example I made in order to explain the problem. I have a Test.c file which depends on a certain file header1.h, which includes another file header2.h. This is the make file:
Test : Test.c header1.h
gcc -o Test Test.c
header1.h : header2.h
The last row is not empty it contains a tab character. Now assume I run make and Test is created. Afterwards I change header2.h. If I run make again, make says that Test is already updated. I expected make to remake Test since header2.h is newer than header1.h.
If I add a trivial recipe to the last rule like this
Test : Test.c header1.h
gcc -o Test Test.c
header1.h : header2.h
echo foo
make behaves as I expected. I also tried adding a semicolon after header2.h in the prerequisite list but this did not help.
You've told make that Test depends on Test.c and header1.h, so it won't run the recipe unless either of the timestamps for those two files are newer than the one for Test.
You could add touch $# as a recipe for header1.h but logically it doesn't really depend on the content of header2.h, Test does, so you should add header2.h as a dependency of Test.
Ideally however you'd avoid manually specifying all this and use GCC's dependency generating flags, you can also take advantage of make's built-in rules, an absolutely minimal example for something like this with a single source file would be
CFLAGS := -MMD
Test:
-include *.d
Others already provided appropriate solutions: Compiler generated dependency files.
This does not answer the part of the question, why adding a "trivial recipe" (echo foo) changes anything. This probably is related to the following make bug.
As OP already found out, the bug can be circumvented by adding a trivial recipe (eg. #true). This causes make to re-evaluate the targets' "timestamp" which is why dependencies are respected expectedly.
I'm supposed to make a Makefile that compiles the source file year.c and after I run it, instead of printing year 2013 it should print 2014. Is there a way to do this without editing the source file?
This creates an intermediate target called c2014.c from your original.c and then compiles that.
.PHONY: all
all: c2014
c2014.c: original.c
sed 's/\<2013\>/2014/' $< >$#
If there are dependencies for original (libraries to link against, etc), then c2014 should depend on those as well.
Different sed versions have slightly different syntax. This assumes that \< and >` match word boundaries.
I have a tool lets say mytool that does some pre-processing on the source files. Basically, it instruments some functions (based on an input list file) in the source files.
The way it is invoked is : (lets say we have two source files - input1.c and input2.c)
./mytool input1.c input2.c --
('--' is for leaving some arguments to default)
Now, I wish to hook this tool to any build process i.e. makefile such that the tool can get all the source files from the makefile and can run on all the source files. So it say there were 3 C files - 1.c, 2.c and 3.c then we would want to do
./mytool 1.c 2.c 3.c --
and then proceed with the usual build process i.e. 'make' in the simplest case.
How can I achieve this? Is this possible by some sort of variable over-riding?
The simplest thing to do, assuming you don't mind the tool running once per .c file (as opposed to once for all .c files) would be to replace the default %: %.c and %.o: %.c built-in make rules (assuming those are in use) and add your tool to the body of those rules.
This only runs the tool for files that need to be re-built from source (as per #Beta's comment on the OP).
Say I have a header file which is included by many source files, maybe with a very deep hierarchy. It is very boring to list this common header file in the prerequisites of each source object, and not sure whether there is an elegant solution. Thanks!
You can generate such dependencies with gcc -M. From TFM:
-M Instead of outputting the result of preprocessing, output a rule suitable for make describing the dependencies of the main source file. The preprocessor outputs one make rule containing the object file name for that source file, a colon, and the names of all the included files, including those coming from -include or -imacros command line options.
Also see Generating Prerequisites Automatically.