I have two files:
main.c will become module calc, it will use API in expression.c.
livepatch-calc.c will become module livepatch-calc.
I have following makefile and work well
obj-m += calc.o
obj-m += livepatch-calc.o
calc-objs += main.o expression.o
ccflags-y := -std=gnu99 -Wno-declaration-after-statement
Currently, I need call expression's API in livepatch-calc.c. So, I have new makefile like:
obj-m += calc.o
obj-m += livepatch-calc.o
calc-objs += main.o expression.o
livepatch-calc-objs += expression.o
ccflags-y := -std=gnu99 -Wno-declaration-after-statement
Unfortunately, when I make it. Warning message show up:
WARNING: modpost: missing MODULE_LICENSE() in ..../livepatch-calc.o
I wondering are there anything wrong in my makefile?
Related
I have some trouble with making Makefile. This is a part of Makefile.
dirs := fwd common bp bp_manager $(XRTE_HASH)
VPATH_ = $(foreach dir,$(dirs),$(SRCDIR)/$(dir))
INC_ = $(foreach dir,$(dirs),$(wildcard $(dir)/*.h))
CFLAGS_ = $(foreach dir,$(dirs),-I$(SRCDIR)/$(dir))
SRCS-y_ = $(foreach dir,$(dirs),$(notdir $(wildcard $(dir)/*.c)))
VPATH += $(VPATH_)
INC += $(INC_)
CFLAGS += $(CFLAGS_)
SRCS-y += $(SRCS-y_)
check:
echo $(CFLAGS)
echo $(SRCS-y)
VPATH and INC worked as I intended.
CFLAGS doesn't contain CFLAGS_
SRCS-y was printed as I inteded, but it has no effect when do "make" - SRCS-y_ was same with null.
CFLAGS and SRCS-y is okay when set manually (without function).
I thought Makefile is almost same with csh.
Can you explain me why the "make" ignores functions?
Thanks.
CFLAGS_ is just a string. $(CFLAGS_) is a variable's value. So you should have:
CFLAGS += $(CFLAGS_)
SRCS-y += $(SRCS-y_)
How do you define multiple variables using make's pattern specific variable values feature https://www.gnu.org/software/make/manual/html_node/Pattern_002dspecific.html#Pattern_002dspecific? For example, suppose that LIBDIR and RPATH have already been defined, and I want to set the following:
LDFLAGS += -L$(LIBDIR) $(RPATH)
LDLIBS += -lsomelibrary
for builds that match the pattern utest%. So for example,
utest% : -L$(LIBDIR) $(RPATH)
would get me halfway there, but then how to define the second variable?
I thought that maybe using multi-line variables https://www.gnu.org/software/make/manual/html_node/Multi_002dLine.html would work, but I can't quite get there. I've tried:
define linking_vars :=
LDFLAGS := -L$(LIBDIR) $(RPATH)
LDLIBS := -lsomelibrary
endef
utest% : $(linking_vars)
and also
define newline =
endef
utest_% : LDFLAGS := -L$(LIBDIR) $(RPATH) $(newline) LDLIBS := -lsomelibrary
but I haven't had any luck yet.
I'm not entirely sure I understand what you want to do, but it sounds as if this might do it:
utest% : LDFLAGS += -L$(LIBDIR) $(RPATH)
utest% : LDLIBS += -lsomelibrary
I am a newbie for Makefile. Optimizing my code Makefile code.
I have following code which is messy, Is there any better way of writing this.(for more clarity added space before each line)
ifdef X
ifndef Y
LNFLAGS + = -m32
else
ifndef Z
LNFLAGS + = -m32
endif
endif
endif
There are a number of questions already on this subject, but despite that and the help on SourceForge, I cannot generate a .gcno or .gcda file.
sample question
2nd question
My make file compiles and runs my unit tests, but does not generate any output files. Is there something obviously wrong here? Commented out lines are things I have tried before.
CPP_PLATFORM = Gcc
#CPP_PLATFORM = Clang
#CPPUTEST_CPPFLAGS += -DSUPPRESS_PRINTING
#CPPUTEST_CPPFLAGS += -fprofile-arcs
#CPPUTEST_CPPFLAGS += -ftest-coverage
#GCOVFLAGS = -fprofile-arcs -ftest-coverage
#CPPUTEST_LDFLAGS += -lssl
#CPPUTEST_LDFLAGS += -lcrypto
#CPPUTEST_LDFLAGS += -fprofile-arcs
CPPUTEST_CPPFLAGS = -DSUPPRESS_PRINTING
CPPUTEST_CPPFLAGS = -fprofile-arcs:$(CPPUTEST_CPPFLAGS)
CPPUTEST_CPPFLAGS = -ftest-coverage:$(CPPUTEST_CPPFLAGS)
CPPUTEST_LDFLAGS = -lssl
CPPUTEST_LDFLAGS = -lcrypto:$(CPPUTEST_LDFLAGS)
CPPUTEST_LDFLAGS = -fprofile-arcs:$(CPPUTEST_LDFLAGS)
CPPUTEST_CPPFLAGS += -g -O0 --coverage
#CPPUTEST_CPPFLAGS += -fprofile-arcs
#CPPUTEST_CPPFLAGS += -ftest-coverage
CPPUTEST_LDFLAGS += -lprofile_rt
Either the -g -O0 --coverage or -fprofile-arcs -ftest-coverage along with the link flag do the trick. The key was the link flag.
I have a makefile that lists the source files: (shortened to relevant)
SRCFOLDER=src/
SOURCES= main.cpp
OBJECTS=$(SOURCES:.cpp=.o)
and I would like to concate the strings together, but for each one in SOURCES. As you can see above, I do it for OBJECTS, but I want to do it like this: (pseudocode)
foreach(src in SOURCES)
src = concate(SRCFOLDER, src)
so that if SOURCES was main.cpp window.cpp, the result would be src/main.cpp src/window.cpp.
I tried this:
SOURCES=$(SOURCES:*=$(SRCFOLDER)/*)
but I get this error:
makefile:12: *** Recursive variable `SOURCES' references itself (eventually). Stop.
SRCFOLDER := src
SOURCES := main.cpp window.cpp
SOURCES := $(addprefix $(SRCFOLDER)/, $(SOURCES))