I am having problems with my makefile
It looks like this
name = project-name
testfiles = $(wildcard tst/*.cxx)
sourcefiles = $(wildcard src/*.cpp)
headerfiles = $(wildcard inc/*.hpp)
tests = $(testfiles:%=%.o)
sources = $(sourcefiles:%=%.o)
headers = $(headerfiles:%=%.gch)
location = /usr/local/include
flags = -Iinc -std=c++17 -pedantic -Wall
all: $(name)
%/:
mkdir -p $#
clean:
rm -f $(tests) $(sources) $(headers) $(name) test
install: $(name)
install $^ $(location)/$<
run-%: %
./$<
test: $(tests)
g++ -o $# $^
$(name): $(sources)
g++ -o $# $^
pch: $(headers)
%.gch: %
g++ -o $# $< $(flags)
tst/catch.cxx.o: tst/catch.cxx inc/catchmain.hpp.gch
g++ -o $# -c $< $(flags)
tst/receive.cxx.o: tst/receive.cxx inc/catchtest.hpp.gch inc/server.hpp.gch
g++ -o $# -c $< $(flags)
src/server.cpp.o: src/server.cpp inc/server.hpp.gch inc/iostream.hpp.gch
g++ -o $# -c $< $(flags)
My folder structure is like this (image attached)
.
├── inc
│ ├── catchmain.hpp
│ ├── catchtest.hpp
│ ├── iostream.hpp
│ └── server.hpp
├── makefile
├── src
│ └── server.cpp
└── tst
├── catch.cxx
└── receive.cxx
And when I run
make test
It shows that it dropped a circular dependency.
I don't see what might cause that.
# The output of `make test`
make: Circular tst/catch.cxx <- tst/catch.cxx.o dependency dropped.
g++ -o inc/catchmain.hpp.gch inc/catchmain.hpp -Iinc -std=c++17 -pedantic -Wall
g++ -o tst/catch.cxx.o -c tst/catch.cxx -Iinc -std=c++17 -pedantic -Wall
make: Circular tst/receive.cxx <- tst/receive.cxx.o dependency dropped.
g++ -o inc/catchtest.hpp.gch inc/catchtest.hpp -Iinc -std=c++17 -pedantic -Wall
g++ -o inc/server.hpp.gch inc/server.hpp -Iinc -std=c++17 -pedantic -Wall
g++ -o tst/receive.cxx.o -c tst/receive.cxx -Iinc -std=c++17 -pedantic -Wall
g++ -o test tst/catch.cxx.o tst/receive.cxx.o
You had Circular dependency because
%: %.o
is a gnu make implicit rule
I just changed the extension from cxx to cpp and everything works without any errors. Weird
Related
I'm trying to create a Makefile for my C++ project, which has the following structure:
root
├── include/
| └──external
| └── stb_image.h
│ └── all .h files here
├── src/
| └── main.cpp
│ └── all .cpp files here
└── Makefile
To compile this project, I'm trying to use the Makefile proposed in this answer, which is for gcc, but I have added CC:=g++ so it should work (I think):
SRC_DIR := src
OBJ_DIR := obj
BIN_DIR := bin
EXE := $(BIN_DIR)/color
SRC := $(wildcard $(SRC_DIR)/*.cpp)
OBJ := $(SRC:$(SRC_DIR)/%.cpp=$(OBJ_DIR)/%.o)
CPPFLAGS := -Iinclude -MMD -MP
CFLAGS := -g -std=c++2a -Wall
LDFLAGS := -Llib
LDLIBS := -lpthread
CC := g++
.PHONY: all clean
all: $(EXE)
$(EXE): $(OBJ) | $(BIN_DIR)
$(CC) $(LDFLAGS) $^ $(LDLIBS) -o $#
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp | $(OBJ_DIR)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
$(BIN_DIR) $(OBJ_DIR):
mkdir -p $#
clean:
#$(RM) -rv $(BIN_DIR) $(OBJ_DIR)
-include $(OBJ:.o=.d)
But when running make I obtain a very long error which I do not understand. I do not know if this error comes from having main.cpp without a main.h.
I need this makefile because I want to separate the declarations and the implementations of my project. Before doing that, I had everything done in headers files and I could compile my project with the following command:
g++ -g -std=c++2a -Wall -Isrc/include -o bin/color.exe src/main.cc -lpthread
Any idea what am I doing wrong? I still do not know a lot about Makefiles, so maybe I'm doing something weird.
I have the following structure for a project and I am just starting to introduce a Makefile to build the software:
├── Makefile
├── README.md
├── cg
│ └── cg.c
└── utilities
├── utilities.c
└── utilities.h
I am trying to put object files in a directory called obj yet I can't seem to get it working.
My makefile looks like:
CC=mpicc
CFLAGS=-O3 -std=c99
LIBS=
MKDIR_P = mkdir -p
make_build_dir:
#mkdir -p obj/
utilities.o: utilities/utilities.c
$(CC) $(CFLAGS) -o ./obj/$# -c $<
cg.o: cg/cg.c
$(CC) $(CFLAGS) -o ./obj/$# -c $<
.PHONY: make_build_dir
cg.exe: make_build_dir utilities.o cg.o
$(CC) $(CFLAGS) -o $# $<
clean:
rm -fr obj
rm cg.exe
Yet this generates the following error:
a#a:b/b ‹master*›$ make cg.exe
mpicc -O3 -std=c99 -o ./obj/utilities.o -c utilities/utilities.c
mpicc -O3 -std=c99 -o ./obj/cg.o -c cg/cg.c
cg/cg.c:133:3: warning: implicit declaration of function 'decompose' is invalid in C99
[-Wimplicit-function-declaration]
decompose(num_chunks, chunks_per_rank,me, &settings);
^
1 warning generated.
mpicc -O3 -std=c99 -o cg.exe make_build_dir
clang: error: no such file or directory: 'make_build_dir'
make: *** [cg.exe] Error 1
How can I get it to generate the object files in the obj directory and then an executable in the top-level directory?
This linking part of the makefile
cg.exe: make_build_dir utilities.o cg.o
$(CC) $(CFLAGS) -o $# $<
has two issues. First, $< refers to the first prerequesite of the target cg.exe, and that is make_build_dir. Declaring it as .PHONY doesn't help here, it's simply passed to $(CC). Second, utilities.o cg.o both don't exist at this location. You can change the rule to
cg.exe: obj/utilities.o obj/cg.o
$(CC) $(CFLAGS) -o $# $^
Note the automatic variable $^ which refers to all prerequisites. Additionally, the object file targets should be
obj/cg.o: cg/cg.c
$(CC) $(CFLAGS) -o $# -c $<
(identical for utilities.o).
First of all, you need to make_build_dir before making any *.o or make won't have a place to put them.
And you can make the Makefile more generic.
.PHONY: all clean info
.DEFAULT_GOAL := all
SRC_DIRS = cg utilities
OBJ_DIR = obj
EXE = cg.exe
SOURCES = $(foreach path, $(SRC_DIRS), $(wildcard $(path)/*.c))
OBJECTS = $(addprefix $(OBJ_DIR)/, $(notdir $(SOURCES:%.c=%.o)))
$(OBJ_DIR)/%.o: */%.c
$(CC) $(CFLAGS) -o $# -c $<
all: make_build_dir $(EXE)
info:
$(info SOURCES=$(SOURCES))
$(info OBJECTS=$(OBJECTS))
make_build_dir:
#mkdir -p $(OBJ_DIR)
$(EXE): $(OBJECTS)
$(CC) $(CFLAGS) -o $# $^
With this Makefile, you can add more source directories to SRC_DIRS and it will automatically compile sources in them.
What does it do? Run make with the -n option to see:
$ make -n
mkdir -p obj
cc -o obj/cg.o -c cg/cg.c
cc -o obj/utilities.o -c utilities/utilities.c
cc -o cg.exe obj/cg.o obj/utilities.o
You can also display the info on the variables by:
$ make info
SOURCES= cg/cg.c utilities/utilities.c
OBJECTS=obj/cg.o obj/utilities.o
Hi I have this makefile:
CC = gcc
AS = nasm
CFLAGS = -ffreestanding -Wall -Wextra -std=c11 -m32 -nostdlib -nostdinc -fno-stack-protector
LDFLAGS = -m elf_i386 -T link.ld
ASFLAGS = -f elf32
SOURCES = $(wildcard src/*.c wildcard src/*.s)
OBJECTS = $(SOURCES:.[s|o]=.o)
INCLUDEPATH = -I inc src/include
OBJDIR = bin/obj
SRCDIR = src/
all: build
build:
ld $(LDFLAGS) $(OBJECTS) -o bin/kernel.bin
iso: build
cp bin/kernel.bin XeonOS/boot
grub-mkrescue -o XeonOS.iso XeonOS/
run: iso
quemu-system-i386 -m 512M -cdrom XeonOS.iso
clean:
rm -rf bin/*.o bin/kernel.bin
%.o: $(SRCDIR)%.c
$(CC) $(INCLUDEPATH) $(CFLAGS) $< -o $(OBJDIR)/$(OBJECTS)
%.o: $(SRCDIR)%.s
$(AS) $(ASFLAGS) $< -o $(OBJDIR)/$(OBJECTS)
And when i execute the command make run i get the following error:
ld -m elf_i386 -T link.ld src/kernel_c.c src/kernel_asm.s -o bin/kernel.bin
ld:src/kernel_c.c: file format not recognized; treating as linker script
Because the kernel_c.c and kernel_asm.s didn' change their extension to .o. How can i change the extension of both .s and .c to .o at the same time?
By the way, I will have another problem, the value of the OBJECTS variable contains the src/ directory but the object files are stored in the bin/obj folder, How can i change that?
When I had this problem last month I just did this:
SOURCES_C := $(wildcard src/*.c)
SOURCES_S := $(wildcard src/*.s)
OBJECTS := $(SOURCES_C:%.c=%.o) \
$(SOURCES_S:%.s=%.o)
I haven't looked at this too deeply but, as far as I know, that's your best bet.
Finally I used the #LightnessRacesinOrbit advice and also used patsubsr so the code is now working:
CC = gcc
AS = nasm
CFLAGS = -m32 -nostdlib -nostdinc -fno-builtin -fno-stack-protector -nostartfiles -nodefaultlibs -Wall -Wextra -Werror
LDFLAGS = -m elf_i386 -T link.ld
ASFLAGS = -f elf32
C_SOURCES = $(wildcard src/*.c)
C_OBJECTS = $(patsubst %.c,%.o, $(notdir $(C_SOURCES) ))
ASM_SOURCES = $(wildcard src/*.s)
ASM_OBJECTS = $(patsubst %.s,%.o, $(notdir $(ASM_SOURCES) ))
INCLUDEPATH = -I src/include
OBJDIR = bin/obj
SRCDIR = src/
.PHONY: build
all: build
build: $(C_OBJECTS) $(ASM_OBJECTS)
ld $(LDFLAGS) $(OBJDIR)/$(ASM_OBJECTS) $(OBJDIR)/$(C_OBJECTS) -o bin/kernel.bin
iso: build
cp bin/kernel.bin XeonOS/boot
grub-mkrescue -o XeonOS.iso XeonOS/
run: iso
bochs -f bochsconfig.cfg -q
clean:
rm -rf XeonOS/boot/kernel.bin
rm -rf bin/obj/*.o bin/kernel.bin
%.o: $(SRCDIR)%.c
$(CC) $(INCLUDEPATH) $(CFLAGS) $< -o $(OBJDIR)/$#
%.o: $(SRCDIR)%.s
$(AS) $(ASFLAGS) $< -o $(OBJDIR)/$#
After a bit of searching, I've managed to throw together the following Makefile:
CC = gcc
CFLAGS = -c -Wall
LDFLAGS =
SOURCEFILES = main.c
SOURCES = src/$(SOURCEFILES)
OBJECTS = $(SOURCES:.c=.o)
EXECUTABLE = netsim
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $#
.c.o:
$(CC) $(CFLAGS) $< -o $#
clean:
rm -rf netsim $(OBJECTS)
I would like to be able to move my object files into another directory, but have been struggling with getting that to work. What am I missing?
The trick is to not move your objects.
You should build it and use it from where they are built.
For example you have the following directory structure:
$ tree .
├── Makefile
├── include
│ └── common_head.h
├── obj
└── src
├── foo.c
└── main.c
Manual execution:
$ gcc -o ./obj/foo.o -c ./src/foo.c -I ./include # Build Object #
$ gcc -o ./obj/main.o -c ./src/main.c -I ./include
$ gcc -o exe ./obj/foo.o ./obj/main.o # Build Executable #
Makefile to simulate the above
C_FLAGS := -g -Wall -Wextra
CC := gcc
RM := rm
LINKFLAGS := -lanylibrary
.PHONY: $(TARGET)
.PHONY: clean
VPATH:= ./src/ ./obj/ ./include/
# Path for .c , .h and .o Files
SRC_PATH := ./src/
OBJ_PATH := ./obj/
INC_PATH := -I ./include
# Executable Name
TARGET := exe
# Files to compile
OBJ1 := foo.o \
main.o
OBJ := $(patsubst %,$(OBJ_PATH)%,$(OBJ1))
# Build .o first
$(OBJ_PATH)%.o: $(SRC_PATH)%.c
#echo [CC] $<
#$(CC) $(C_FLAGS) -o $# -c $< $(INC_PATH)
# Build final Binary
$(TARGET): $(OBJ)
#echo [INFO] Creating Binary Executable [$(TARGET)]
#$(CC) -o $# $^ $(LINKFLAGS)
# Clean all the object files and the binary
clean:
#echo "[Cleaning]"
#$(RM) -rfv $(OBJ_PATH)*
#$(RM) -rfv $(TARGET)
So when you do a Make
$ make -B
[CC] src/foo.c
[CC] src/main.c
[INFO] Creating Binary Executable [exe]
To see a dry-run use make -n
$ make clean ; make -n
g++ -g -Wall -Wextra -o obj/foo.o -c src/foo.c -I ./include
g++ -g -Wall -Wextra -o obj/main.o -c src/main.c -I ./include
g++ -o exe obj/foo.o obj/main.o -lanylibrary
So after building your directory structure should look like this.
$ tree .
├── Makefile
├── exe
├── include
│ └── common_head.h
├── obj
│ ├── foo.o
│ └── main.o
└── src
├── foo.c
└── main.c
So from my previous answer.
You don't have to use any PHONY move and also no objects are recreated unnecessarily.
Something like this?
SOURCES = src/main.c
OBJECTS = obj/main.o
...
obj/%.o: src/%.c
$(CC) $(CFLAGS) $< -o $#
Once that's working, you can add further tricks, like this:
OBJECTS = $(patsubst src/%.c, obj/%.o, $(SOURCES)
I have the following Makefile
CXX = g++
CXXFLAGS = -g -Wall
COMPILE = ${CXX} ${CXXFLAGS} -c
LINK = ${CXX} -lpthread
LIB_INC = -Ilib -Iwrappers -Iprocesses
src := $(wildcard lib/*.cpp) $(wildcard wrappers/*.cpp)
obj = $(src:.cpp=.o)
src_1 := processnetwork_part001.cpp sc_application_1.cpp
obj_1 = $(src_1:.cpp=.o)
src_2 := processnetwork_part002.cpp sc_application_2.cpp
obj_2 = $(src_2:.cpp=.o)
all : sc_application_1 sc_application_2
.PHONY : all
sc_application_1 : ${obj} ${obj_1}
${LINK} -o sc_application_1 $(obj) ${obj_1}
sc_application_2 : ${obj} ${obj_2}
${LINK} -o sc_application_2 $(obj) ${obj_2}
%.o : %.cpp %.h
${COMPILE} -o $# $< $(LIB_INC)
clean :
rm sc_application_1 sc_application_2 ${obj} ${obj_1} ${obj_2}
Where lib, wrappers and processes are subdirectories of the directory where the Makefile and the two main applications sc_application_1 and sc_application_2 are stored. When I run make, I get the following output (only the last few lines w/o compiler warnings).
g++ -g -Wall -c -o lib/Scheduler.o lib/Scheduler.cpp -Ilib -Iwrappers -Iprocesses
g++ -g -Wall -c -o wrappers/consumer_wrapper.o wrappers/consumer_wrapper.cpp -Ilib -Iwrappers -Iprocesses
g++ -g -Wall -c -o wrappers/generator_wrapper.o wrappers/generator_wrapper.cpp -Ilib -Iwrappers -Iprocesses
g++ -g -Wall -c -o wrappers/square_wrapper.o wrappers/square_wrapper.cpp -Ilib -Iwrappers -Iprocesses
g++ -g -Wall -c -o processnetwork_part001.o processnetwork_part001.cpp -Ilib -Iwrappers -Iprocesses
g++ -g -Wall -c -o sc_application_1.o sc_application_1.cpp
In file included from wrappers/wrappers.h:4:0,
from sc_application_1.cpp:10:
wrappers/generator_wrapper.h:4:28: fatal error: ProcessWrapper.h: No such file or directory
compilation terminated.
make: *** [sc_application_1.o] Error 1
Compilation fails because for some reason that I don't understand, the variable LIB_INC isn't added anymore to
g++ -g -Wall -c -o sc_application_1.o sc_application_1.cpp
But it is (as I intended) on all previous lines. Can anyone explain me this behaviour? Thank you.
edit: The error doesn't occur when I ommit the "%.h" in the "%.o" target.
I'm going to go out on a limb, and guess that there is no sc_application_1.h, but there is a header file for every previous source (e.g. Scheduler.h, consumer_wrapper.h ...).
Your %.o: %.cpp %.h rule doesn't apply if there is no %.h, so Make falls back on its default rule, which does not use LIB_INC. The simplest way to fix this is to add another %.o rule:
%.o : %.cpp %.h
${COMPILE} -o $# $< $(LIB_INC)
%.o : %.cpp
${COMPILE} -o $# $< $(LIB_INC)