while preparing for a project about digital circuit class, I have a question about reading lines from 'input.txt' to writing lines at 'output.txt'.
I was intend to copy the 'input.txt' lines to 'output.txt' lines. However, there was unintended integers at the 'output.txt'. My codes are below.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;
entity TOP_Xray_cnn is
port( clk: in std_logic);
end TOP_Xray_cnn;
architecture Behavioral of TOP_Xray_cnn is
begin
process(clk)
file inFile : text open read_mode is "input.txt";
file outFile: text open write_mode is "output.txt";
variable line_in : line;
variable line_out : line;
variable data_in : integer;
variable data_out : integer;
begin
if rising_edge(clk) then
while not(endfile(inFile)) loop
readline(inFile, line_in);
read(line_in, data_in);
data_out := data_in + 1;
write(line_out, data_out);
writeline(outFile, line_out);
end loop;
end if;
file_close(inFile);
file_close(outFile);
end process;
end Behavioral;
Input.txt
1
2
3
4
5
output.txt
22
3
4
5
6
what happen to the first row of output.txt file?
why are there two '2' which I intend one '2' ??
Related
I am trying to read an image file using textio package in vhdl.
If i open an .jpg with notepad , i will get some junk data but actually it is ASCII data . Here i am trying to read these ascii data and convert them into bytes.
below is my code:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity file_io is
port (
clk: in std_logic;
Data: out std_logic_vector(7 downto 0)
);
end entity;
architecture behav of file_io is
signal test_data : std_logic_vector(7 downto 0);
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
begin
File_reader:process(clk)
file f : text open read_mode is "C:\Users\Public\Pictures\Sample Pictures\Chrysanthemum.jpg";
variable L: line;
variable var_int: integer:= 0;
variable var_char: character;
begin
if rising_edge(clk) then
while not endfile(f) loop
readline(f, L);
read(L, var_char);
var_int := character'pos(var_char);
test_data <= std_logic_vector(to_unsigned(var_int, test_data'length));
end loop;
end if;
Data <= test_data;
end process;
end architecture behav;
testbench:
LIBRARY ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
ENTITY file_io_test IS
END file_io_test;
ARCHITECTURE behavior OF file_io_test IS
use work.io.all;
signal clk: std_logic := '0';
signal Data: std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
UUT:
entity work.file_io(behav)
port map (
clk => clk,
Data => Data
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '1';
wait for clk_period/2; --for 5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 5 ns signal is '0'.
end process;
end behavior;
I am getting only one byte in waveform. expected result is : Every clock cycle new character should be rread and new byte should be obtained.
below is waveform:
below is the image I am trying to read:
You have a while loop placed inside the rising_edge part of your process. What happens is that when the first clock edge occurs, the while loop iterates until the end of the file and gives you the last byte of the input image.
Removing the while loop statement should solve your issue.
The question has a fundamental flaw. You can't use textio to read binary values, it's for text.
See IEEE Std 1076-2008 16.4 Package TEXTIO paragraphs 3 (in part) and 4:
Procedures READLINE, WRITELINE, and TEE declared in package TEXTIO read and write entire lines of a file of type TEXT. Procedure READLINE causes the next line to be read from the file and returns as the value of parameter L an access value that designates an object representing that line. If parameter L contains a non-null access value at the start of the call, the procedure may deallocate the object designated by that value. The representation of the line does not contain the representation of the end of the line. ...
The language does not define the representation of the end of a line. An implementation shall allow all possible values of types CHARACTER and STRING to be written to a file. However, as an implementation is permitted to use certain values of types CHARACTER and STRING as line delimiters, it might not be possible to read these values from a TEXT file.
And that can be demonstrated with your Chrysanthemum.jpg:
It is possible in VHDL to read raw characters one at a time (matching your need).
See IEEE Std 1076-2008 5.5 File types:
So all we have to do is declare a file type and we get these procedures defined implicitly.
We can use them to invoke raw read, without any end of line issues caused by textio:
library ieee;
use ieee.std_logic_1164.all;
entity file_io is
port (
clk: in std_logic;
Data: out std_logic_vector(7 downto 0);
done: out boolean
);
end entity;
architecture foo of file_io is
use ieee.numeric_std.all;
begin
File_reader:
process (clk)
-- "C:\Users\Public\Pictures\Sample Pictures\Chrysanthemum.jpg";
constant filename: string := "Chrysanthemum.jpg"; -- local to sim
variable char_val: character;
variable status: FILE_OPEN_STATUS;
variable openfile: boolean; -- FALSE by default
type f is file of character;
file ffile: f;
variable char_count: natural := 0;
begin
if rising_edge (clk) then
if not openfile then
file_open (status, ffile, filename, READ_MODE);
if status /= OPEN_OK then
report "FILE_OPEN_STATUS = " &
FILE_OPEN_STATUS'IMAGE(status)
severity FAILURE;
end if;
report "FILE_OPEN_STATUS = " & FILE_OPEN_STATUS'IMAGE(status);
openfile := TRUE;
else
if not endfile(ffile) then
read(ffile, char_val);
-- report "char_val = " & character'image(char_val);
char_count := char_count + 1;
Data <= std_logic_vector (
to_unsigned(character'pos(char_val),
Data'length) );
end if;
if endfile(ffile) then -- can occur after last character
report "ENDFILE, read " &
integer'image(char_count) & "characters";
done <= TRUE;
FILE_CLOSE(ffile);
end if;
end if;
end if;
end process;
end architecture foo;
library ieee;
use ieee.std_logic_1164.all;
entity file_io_test is
end file_io_test;
architecture behavior of file_io_test is
signal clk: std_logic := '0';
signal data: std_logic_vector(7 downto 0);
signal done: boolean;
constant clk_period: time := 10 ns;
begin
uut:
entity work.file_io(foo)
port map (
clk => clk,
data => data,
done => done
);
clk_process:
process
begin
if not done then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process;
end architecture behavior;
Now we can have all the characters than can delimit a line show up in our read:
Note that package std.textio is not made visible through any context item.
I have a file source.txt, it looks like this:
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
0065006500660067006700690069006A006B006C006E
00650065006600670067006700680069006A006C006D
00650065006600670067006600660068006A006B006D
006500650066006700670065006600670069006B006D
00650065006600670067006600670068006A006C006D
0065006500660067006700690069006A006B006C006E
*
After each line there is the hidden newline character '\n'.
The asterix '*' is my visible end-of-file character.
How do I write a testbench in VHDL that does the following:
read file
store one line in a vector
write that vector in a new target.txt
Using VHDL-2008, and showing the std_logic_vector underway, the code can be:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity tb is
end entity;
architecture syn of tb is
begin
process is
variable line_v : line;
file read_file : text;
file write_file : text;
variable slv_v : std_logic_vector(44 * 4 - 1 downto 0);
begin
file_open(read_file, "source.txt", read_mode);
file_open(write_file, "target.txt", write_mode);
while not endfile(read_file) loop
readline(read_file, line_v);
hread(line_v, slv_v);
report "slv_v: " & to_hstring(slv_v);
hwrite(line_v, slv_v);
writeline(write_file, line_v);
end loop;
file_close(read_file);
file_close(write_file);
wait;
end process;
end architecture;
is it possible to write a module code for a test bench? I have a test bench code that reads a text file and shows it in the Isim but I want to put this data on a port and process it. how can I get it out of simulation environment? how can I write a module for that in VHDL? thank you
, the code is here:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all; --Dont forget to include this library for file operations.
ENTITY read_file IS
END read_file;
ARCHITECTURE beha OF read_file IS
signal bin_value : std_logic_vector(2 downto 0):="000";
BEGIN
--Read process
process
file file_pointer : text;
variable line_content : string(1 to 3);
variable line_num : line;
variable j : integer := 0;
variable char : character:='0';
begin
--Open the file read.txt from the specified location for reading(READ_MODE).
file_open(file_pointer,"C:\read.txt",READ_MODE);
while not endfile(file_pointer) loop --till the end of file is reached continue.
readline (file_pointer,line_num); --Read the whole line from the file
--Read the contents of the line from the file into a variable.
READ (line_num,line_content);
--For each character in the line convert it to binary value.
--And then store it in a signal named 'bin_value'.
for j in 1 to 3 loop
char := line_content(j);
if(char = '0') then
bin_value(3-j) <= '0';
else
bin_value(3-j) <= '1';
end if;
end loop;
wait for 10 ns; --after reading each line wait for 10ns.
end loop;
file_close(file_pointer); --after reading all the lines close the file.
wait;
end process;
end beha;
I want to read 32bit signed number from a text file and store that in a variable. I have program for integer read but it is not working for std_logic_vector type.
With VHDL-2008, it can be done like:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
architecture syn of tb is
begin
process is
file txt_file : text;
variable line_v : line;
variable slv_v : std_logic_vector(31 downto 0);
variable good_v : boolean;
begin
-- Write text file with std_logic_vector
file_open(txt_file, "test.txt", write_mode);
slv_v := X"1234" & "XXXXXXXX" & "ZZZZZZZZ" ;
write(line_v, slv_v);
writeline(txt_file, line_v);
file_close(txt_file);
-- Read text file with std_logic_vector
file_open(txt_file, "test.txt", read_mode);
readline(txt_file, line_v);
report "line_v: " & line_v.all;
read(line_v, slv_v, good_v);
file_close(txt_file);
-- Done
wait;
end process;
end architecture;
The "test.txt" text file then contains:
0001001000110100XXXXXXXXZZZZZZZZ
With VHDL-2002, the std_logic_vector is not supported in write/read procedures, but the Synopsys package ieee.std_logic_textio can be used to provide procedures with:
use ieee.std_logic_textio.all;
I found this code which is a part of Exponentiation implementation, I believe this code is for parallel load register, the code had many mistakes, yet I tried to fix it and simplify it(simplification is to make it work), the original code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG is --Register entity
Port ( CLK,set,reset,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Din_s: in std_logic;
Dout: out std_logic);
end REG;
architecture behavior of REG is
signal Q_temp: std_logic_vector(m-1 down to 0);
begin
Dout<=”0”;
comb:process(In_LOAD,Din_s)
begin
if(In_LOAD=”1”) then Q_temp<=Din_p;end if;
end process comb;
state: process(CLK,set,reset)
begin
if(reset=”1”) then Q_temp<=(others=>”0”);end if;
if(set=”1”) then Q_temp<= (others=>”1”);
elsif(CLK’event and CLK=”1”) then
Q_temp:=Din_p & Q_temp(m-1 down to 1);
end if;
Dout<= Q_temp(0);
end process state;
end behavior;
while the code I modified is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG2 is --Register entity
generic (m: integer := 4);
Port ( CLK,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Dout: out std_logic);
end REG2;
architecture behavior of REG2 is
signal Q_temp: std_logic_vector(m-1 downto 0);
begin
Dout<='0';
process(In_LOAD, Din_p, CLK)
begin
if (CLK'event and CLK='1') then
Q_temp <=Din_p;
elsif (In_LOAD='1') then
Q_temp <= Din_p & Q_temp(m-1 downto 1);
end if;
end process;
Dout <= Q_temp(0);
end behavior;
so my questions are : 1- why I'm getting this error :(Error (10344): VHDL expression error at REG2.vhd(18): expression has 0 elements, but must have 4 elements)?
2- this is a code for parallel load register, right?
thx
Plenty of things are wrong with your code (and the original code).
use the correct quote character " for bit strings and ' for bits instead of ”
downto is one word, not down to
m is not declared; perhaps this is supposed to be a generic?
Assign to Q_temp using signal assignment <= instead of variable assignment :=
Sensitivity lists for both your processes are incomplete
As #Morten mentions: the direction of Din_p should probably downto instead of to
Bonus (pet peeve): don't use IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED, because they are not properly standardized. Use ieee.numeric_std instead.