How to test bench VHDL signals and show them In GTKWAVE? - vhdl

Question

I emulated this VHDL code using GHDL in terminal, no errors occured, but when I imported .vcd file into GTKWAVE no signal shown up.
SCREENSHOT OF GTKWAVE
Desing Code:
Library ieee; Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
entity EXO is
port (CLK, EN: in bit; SORTIE: out bit);
end entity;
architecture EXXO of EXO is
signal compt : integer range 0 to 7 ;
signal etat : bit;
begin
process (CLK)
begin
if CLK'event and CLK = '1' then
if EN = '1' then
compt <= compt + 1;
case etat is
when '0' => if compt = 3 then compt <= 0; SORTIE <= '1'; etat <= '1'; end if;
when '1' => if compt = 2 then compt <= 0; SORTIE <= '0'; etat <= '0'; end if;
end case;
end if;
end if;
end process;
end architecture;
EDIT: I am new to VHDL, so please bear with me.
I am required to complete this
chronogram. The design code is given. I tried to create a Test bench for it, and here is the result:
GTKWAVE Screenshot 2 Which is obviously an utter failure (Failed to show compt, etat, SORTIE).
Test Bench:
Library ieee; Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
entity EXOtb is
end entity;
architecture EXXOtb of EXOtb is
component EXO
port (CLK, EN: in bit; SORTIE: out bit);
end component;
signal CLKtb, ENtb: bit;
signal SORTIEtb: bit;
begin
DUT: EXO port map (CLK => CLKtb, EN => ENtb, SORTIE => SORTIEtb );
STIMULUS: process
begin
CLKtb <= '0'; ENtb <= '0'; wait for 10 ns;
CLKtb <= '0'; ENtb <= '1'; wait for 10 ns;
CLKtb <= '1'; ENtb <= '1'; wait for 10 ns;
CLKtb <= '1'; ENtb <= '1'; wait for 10 ns;
assert false report "Reached End of test";
wait;
end process;
end architecture;
EDIT 3: Thanks to #user1155120's detailed answer, I believe I have solved the problem.
Instead of declaring CLK values manually, I have created a proper function for it.
For some reason, in order to show internal signals in GTKWAVE, You need to declare them as well in the test bench, honestly I don't know why.
By looking carefully into the design code, the input EN seems to refer to some enabling property, and the code runs only if EN is true, so in the test bench I gave it the value of 1. Also, that if EN = '1' then seems to be redundant and there is no need for since EN is always 1. I kept it as it is though.
The new Design Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity EX is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
SORTIE : out STD_LOGIC);
end EX;
architecture Behavioral of EX is
signal compt : integer range 0 to 7 ;
signal etat : bit;
begin -- Stimulus process
process (CLK)
begin
if CLK'event and CLK = '1' then
if EN = '1' then
compt <= compt + 1;
case etat is
when '0' => if compt = 3 then compt <= 0; SORTIE <= '1'; etat <= '1'; end if;
when '1' => if compt = 2 then compt <= 0; SORTIE <= '0'; etat <= '0'; end if;
end case;
end if;
end if;
end process;
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY EXTB IS
END EXTB;
ARCHITECTURE behavior OF EXTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EX
PORT(
CLK : IN std_logic;
EN : IN std_logic;
SORTIE : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal EN : std_logic := '1';
-- Inner
signal compt : integer range 0 to 7 ;
signal etat : bit;
--Outputs
signal SORTIE : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EX PORT MAP (
CLK => CLK,
EN => EN,
SORTIE => SORTIE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
process (CLK)
begin
if CLK'event and CLK = '1' then
if EN = '1' then
compt <= compt + 1;
case etat is
when '0' => if compt = 3 then compt <= 0; SORTIE <= '1'; etat <= '1'; end if;
when '1' => if compt = 2 then compt <= 0; SORTIE <= '0'; etat <= '0'; end if;
end case;
end if;
end if;
end process;
END;
GTKWAVE result (All signals are shown as required in the homework)