In a GNU makefile, I need to rename
/infiles/signal_*.wav
to
/outfiles/out_signal_*.wav
This works (using subst):
SIGNALIN += $(wildcard /infiles/signal_*.wav)
TEMP += $(subst infiles,outfiles, $(SIGNALIN) )
SIGNALOUT += $(subst signal,out_signal, $(TEMP) )
Is there a better, one-line way that would not include the TEMP line?
You can wrap function calls:
SIGNALOUT += $(subst signal,out_signal,$(subst infiles,outfiles,$(SIGNALIN)))
In your case there are not really replacements at two places. What you want is replace /infiles/ at the beginning of each word by /outfiles/out_. And that's one place. Try:
SIGNALOUT := $(patsubst /infiles/%,/outfiles/out_%,$(SIGNALIN))
Related
We are facing a slightly weird problem in GNU Make.
In one of the part Makefile, we try to modify a string in order to get right filename.
So "dummy_1_.pl" is to converted to "dummy_1.pl".
We tried to use following way :-
MY_STRING := dummy_1_.pl
UNDPL := _.pl
DPL := .pl
$(subst $(UNDPL), $(DPL), $(MY_STRING) )
Surprisingly it doesn't work. We can replace ".", "pl", ".pl" etc all this way. However just "" or "." or "_.pl" etc replacement strings starting with an underscore doesn't seem to work.
Is underscore a special character in Make. Are we missing something basic here... We are at GNU Make 3.81
Any help/thought is highly appreciated. Thanks in advance!.
EDIT :-
The problem was posted in short for focused discussion. It seems, the details are necessary. This applies to a pattern rule as below. There's a OUT_V_FILES target that contains *blah_cpu.v *foo_gpu.v etc various target files. (The special string "cpu", "gpu" etc are part of a list.) We want to derive blah.pl, foo.pl respectively as input file for the rule.
DEVICES := cpu gpu memc dram
MY_STRING := $$(foreach dev,$(DEVICES),$$(subst $$(dev),$(NOTHING),$$(notdir %.pl)))
NOTHING :=
UDOT := _.
DOT := .
$(OUT_V_FILES) : %.v : $(subst $(UDOT),$(DOT),S(MY_STRING)) Makefile
#Body of rule+++++++++
There are two problems here. 1) you never assign the result of the $(subst ... invocation and 2) you have to be aware that whitespace is significant within the context of string manipulation functions. With that in mind your makefile code should be something like...
MY_STRING := $(subst $(UNDPL),$(DPL),$(MY_STRING))
In your updated example, it looks like you have some issues when setting MY_STRING. If you correct it to have the proper filename(s), you get:
MY_STRING := $$(foreach dev,$(DEVICES),$$(subst $$(dev),$(NOTHING),$$(notdir %.pl)))
$(info 1. MY_STRING=$(MY_STRING))
MY_STRING := dummy_1_.pl
$(info 2. MY_STRING=$(MY_STRING))
NOTHING :=
UDOT := _.
DOT := .
MY_NEW_STRING=$(subst $(UDOT),$(DOT),$(MY_STRING))
$(info MY_NEW_STRING=$(MY_NEW_STRING))
gives
1. MY_STRING=$(foreach dev,cpu gpu memc,$(subst $(dev),,$(notdir %.pl)))
2. MY_STRING=dummy_1_.pl
MY_NEW_STRING=dummy_1.pl
I want to filter out a pattern as "-Wl, Bdynamic -lmylib" from a long LDFLAGS list. But filter-out function can only handle space-separated list, is there other method to do this in Makefile?
The only way to do it is by replacing spaces with some other character that you know doesn't appear in the variable value. For example suppose you know that the ^ character never appears in your variable value, then you can do something like this:
# Create a variable containing a space
E :=
S := $E $E
LDFLAGS := $(subst ^,$S,$(subst -Wl^Bdynamic^-lmylib,,$(subst $S,^,$(LDFLAGS))))
Given the following GNU Makefile code.
ENDING = '\.cpp'
OBJ = $(SOURCES:$(ENDING)=.o) # (does not work)
This does replace nothing, however,
OBJ = $(SOURCES:.cpp=.o)
does (for cpp files). Is there a way to tell patsubst specific endings? Or at least to replace all kind of endings, like below?
OBJ = $(SOURCES:.*=.o) # (does not work)
This works:
ENDING = .cpp
OBJ = $(SOURCES:$(ENDING)=.o)
And this will replace all endings:
OBJ = $(addsuffix .o,$(basename $(SOURCES)))
I wonder how to match exact occurrence of a given word in the given list of words using only standard makefile operations. In the below example for WORD_TO_MATCH = a the result is positive and apparently wrong.
INPUT_LIST= aa bb
WORD_TO_MATCH = aa
#WORD_TO_MATCH = a
ifneq ($(findstring $(WORD_TO_MATCH),$(INPUT_LIST)),)
$(warning List contains "$(WORD_TO_MATCH)")
else
$(warning List doesnt contain "$(WORD_TO_MATCH)")
endif
Use filter instead of findstring:
...
ifneq ($(filter $(WORD_TO_MATCH),$(INPUT_LIST)),)
$(warning List contains "$(WORD_TO_MATCH)")
...
I have a list of file path like that:
FILE_PATH := a1.so a2.so bla/a3.so bla/a3.so bla/blo/a4.so....
I need to add a prefix to the basename in order to get:
FILE_PATH_PREFIXED := liba1.so liba2.so bla/liba3.so bla/liba3.so bla/blo/liba4.so....
any idea?
Look at Make's addsuffix function.
Here is an example we use with `addsuffix` to place obj files one directory below
the source.
SOURCE += MainThread.cpp
SOURCE += Blah.cpp
OBJ=$(join $(addsuffix ../obj/, $(dir $(SOURCE))), $(notdir $(SOURCE:.cpp=.o)))
From the make manual:
$(addprefix prefix,names...)
The argument names is regarded as a series of names, separated by
whitespace; prefix is used as a unit. The value of prefix is
prepended to the front of each individual name and the resulting
larger names are concatenated with single spaces between them. For
example,
$(addprefix src/,foo bar)
produces the result src/foo src/bar.