GNU make linker input file unused because linking not done - makefile

Question

I have some troubles with my make file. All the output files are generated, but linking is not possible. Therefore, I don't get the output executable. Where is my mistake?
Here is my recipe for the output file:
gcc main.o memory.o startup_msp432p401r_gcc.o system_msp432p401r.o interrupts_msp432p401r_gcc.o -Wall -Werror -g -O0 -std=c99 -DHOST -MM -Wl,-Map=c1m2.map -T msp432p401r.lds -o c1m2.out
And here is the whole makefile:
ifeq ($(PLATFORM),HOST)
CC = gcc
else
CC = arm-none-eabi-gcc
endif
# Architectures Specific Flags
LINKER_FILE = msp432p401r.lds
CPU = cortex-m4
ARCH = mthumb
SPECS = nosys.specs
# Compiler Flags and Defines
LD = arm-none-eabi-ld
ifeq ($(PLATFORM),MSP432)
CFLAGS = -Wall -Werror -g -O0 -std=c99 -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 --specs=nosys.specs
LDFLAGS = -T msp432p401r.lds
else
CFLAGS = -Wall -Werror -g -O0 -std=c99 -DHOST
LDFLAGS = -Wl,-Map=$(TARGET).map -T msp432p401r.lds
endif
TARGET = c1m2
CPPFLAGS = -MM
OBJS = $(SOURCES:.c=.o)
%.o: %.c
$(CC) $< $(CFLAGS) $(CPPFLAGS) -o $#
.PHONY: build
build: all
.PHONY: all
all: $(TARGET).out
$(TARGET).out: $(OBJS)
$(CC) $(OBJS) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -o $#
.PHONY: clean
clean:
rm -f $(OBJS) $(TARGET).out $(TARGET).map
Thank you very much!