I'm using Quartus Prime Lite Edition and I want to use unary operator nand on std_logic_vector like this
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity example1 is
port(
BIN : in std_logic_vector (7 downto 0);
result : out std_logic
);
end;
architecture Beh of example1 is
begin
result <= nand BIN;
end Beh;
I tried to follow this instructions, changed VHDL version under VHDL Input in Compiler Settings. Still no effect and getting:
Error (10500): VHDL syntax error at lab2.vhd(16) near text "nand"; expecting "(", or an identifier ("nand" is a reserved keyword), or unary operator
Quartus Prime Lite does not support VHDL 2008.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf
This error is coming as "nand" requires two inputs.
From your question, it appears to me that you want to perform the bitwise nand operation on the input.
If yes, you can replace architecture as follows. I am assuming that you are familiar with the "generate for" syntax!
architecture Beh of example1 is
--Signals for Storing Intermediate Bitwise Values
signal temp1:std_logic_vector(3 downto 0);
signal temp2:std_logic_vector(1 downto 0);
begin
-- First level of NAND Operations
label_1: for i in 0 to 3 generate
temp1(i)<=BIN(2*i) nand BIN(2*i+1);
end generate label_1;
-- Second level of NAND Operations
label_2: for j in 0 to 1 generate
temp2(j)<= temp1(2*j) nand temp1(2*j+1);
end generate label_2;
-- Getting the Final Output
result<= temp2(1) nand temp2(0);
end Beh;
Thanks,
Dr. Ray
Related
I designed a simple shifter but I got an error, I applied different lots of things to solve, then it hasn't been fixed.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
--use ieee.std_logic_unsigned.all;
entity shifter is
Port ( inp : in STD_LOGIC_VECTOR(7 downto 0);
shift_cntrl : in STD_LOGIC_VECTOR(1 downto 0);
shift_out : out STD_LOGIC_VECTOR(15 downto 0));
end shifter;
architecture Behavioral of shifter is
begin
process(shift_cntrl, inp) begin
with shift_cntrl select
shift_out <= STD_LOGIC_VECTOR(to_unsigned(inp, shift_out'LENGTH) sll 4) when "01",
STD_LOGIC_VECTOR(to_unsigned(inp, shift_out'LENGTH) sll 8) when "10",
inp when others;
end process;
end Behavioral;
VHDL error messages:
[Synth 8-2778] type error near inp ; expected type natural [shifter.vhd:18]
[Synth 8-2778] type error near inp ; expected type natural [shifter.vhd:19]
[Synth 8-2757] this construct is only supported in VHDL 1076-2008 [shifter.vhd:20]
with..select is only supported inside a process when the file mode is set to VHDL 2008. Either set the file mode in Vivado to 2008 or simply remove the process around the with..select statement as it is not needed.
In addition, there is no function to_unsigned for a std_logic_vector. Because it is a similar type, you can do a type conversion:
STD_LOGIC_VECTOR(unsigned(inp) sll 4);
I expect the following code to simply generate two AND gates, but the gate of the procedure gets a latch at the output. In my original code, removing (commenting) the direct path gets rid of the latch, but I haven't been able to isolate this.
What causes this latch, and how can it be avoided?
Note that this is a purely combinatorial circuit without ifs and such generally associated with latch inference.
I am using Vivado 2018.3 on Linux Mint 19.
Edit 1: putting the direct path in a process statement gets rid of the latch.
Edit 2: the latch is no longer there after synthesis, so it can (probably) not cause problems. The question remains why it is generated in the first place.
library IEEE;
use IEEE.std_logic_1164.all;
entity mcve is
port (
a, b : in std_logic;
o : out std_logic_vector(1 downto 0)
);
end entity;
architecture rtl of mcve is
procedure and_proc (signal pa, pb : in std_logic; signal po : out std_logic) is
begin
po <= pa and pb;
end procedure;
begin
o(0) <= a and b;
and_proc(a, b, o(1));
end architecture;
I am trying to create a "dynamic" 2D array which I can set with generics in my entity.
I followed the example in https://s3.amazonaws.com/verificationhorizons.verificationacademy.com/volume-8_issue-3/articles/stream/vhdl-2008-why-it-matters_vh-v8-i3.pdf on page 32.
The declaration of my type within the package (TypeDeclarations):
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package TypeDeclarations is
-- Type BusArray -----------------------------------------------------
-- Can be used by: DArray((Y - 1) downto 0)((X - 1) downto 0); --
--
type TArray is array (natural range <>) of std_logic_vector; --
--
----------------------------------------------------------------------
end package;
my entity:
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
-- Own libraries
use work.TypeDeclarations.all;
entity DynamicRegisterSet is
generic (
INPUT_DATAWIDTH : integer := 1;
OUTPUT_DATAWIDTH : integer := 8;
N_REGISTERS : integer := 1);
port (
MCLK : in std_logic := '0';
WE : in std_logic := '0';
-- input data
DATA : in std_logic_vector((INPUT_DATAWIDTH-1) downto 0) := (others => '0');
SEL : in integer range 0 to (INPUT_DATAWIDTH-1) := 0;
-- in/output data (register set)
REGISTERSET : inout TArray((N_REGISTERS-1) downto 0)((OUTPUT_DATAWIDTH-1) downto 0) := (others => (others => '0')));
end DynamicRegisterSet;
This is the first time I'm using the updated compiler (VHDL200X), I don't think I am doing this wrong but else I wouldn't get this message:
VHDL\CommonBlocks\DynamicRegisterSet\Sources\DynamicRegisterSet.vhd" Line 25: Illegal syntax for subtype indication
Anyone any suggestions? I would appreciate it very much, thanks!
Xilinx ISE 14.7 has no VHDL-2008 support...
They support a hand full of VHDL-2002/2008 features, but unconstrained array elements are not supported.
Vivado added VHDL-2008 support in 2016.1 and sets it as default. But as far as I can see, it's no full VHDL-2008 support.
There is a Xilinx XST synthesis user guide listing these features in the VHDL section. (Sorry I don't have the UG number on my phone.)
ISE
ISE has no VHDL-2008 support at all. Read more details on Xilinx forum or from XST guide ISE12 ISE14
Supported VHDL IEEE Standards
XST supports the following VHDL IEEE standards:
Std1076-1987
Std1076-1993
Std1076-2006
Note Std 1076-2006 is only partially implemented.
Vivado
Vivado has a set of synthetisable VHDL-2008 construct. Read more details in UG901
(Supported VHDL-2008 features chapter)
I found this code which is a part of Exponentiation implementation, I believe this code is for parallel load register, the code had many mistakes, yet I tried to fix it and simplify it(simplification is to make it work), the original code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG is --Register entity
Port ( CLK,set,reset,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Din_s: in std_logic;
Dout: out std_logic);
end REG;
architecture behavior of REG is
signal Q_temp: std_logic_vector(m-1 down to 0);
begin
Dout<=”0”;
comb:process(In_LOAD,Din_s)
begin
if(In_LOAD=”1”) then Q_temp<=Din_p;end if;
end process comb;
state: process(CLK,set,reset)
begin
if(reset=”1”) then Q_temp<=(others=>”0”);end if;
if(set=”1”) then Q_temp<= (others=>”1”);
elsif(CLK’event and CLK=”1”) then
Q_temp:=Din_p & Q_temp(m-1 down to 1);
end if;
Dout<= Q_temp(0);
end process state;
end behavior;
while the code I modified is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG2 is --Register entity
generic (m: integer := 4);
Port ( CLK,In_LOAD : in std_logic;
Din_p: in std_logic_vector(m-1 to 0);
Dout: out std_logic);
end REG2;
architecture behavior of REG2 is
signal Q_temp: std_logic_vector(m-1 downto 0);
begin
Dout<='0';
process(In_LOAD, Din_p, CLK)
begin
if (CLK'event and CLK='1') then
Q_temp <=Din_p;
elsif (In_LOAD='1') then
Q_temp <= Din_p & Q_temp(m-1 downto 1);
end if;
end process;
Dout <= Q_temp(0);
end behavior;
so my questions are : 1- why I'm getting this error :(Error (10344): VHDL expression error at REG2.vhd(18): expression has 0 elements, but must have 4 elements)?
2- this is a code for parallel load register, right?
thx
Plenty of things are wrong with your code (and the original code).
use the correct quote character " for bit strings and ' for bits instead of ”
downto is one word, not down to
m is not declared; perhaps this is supposed to be a generic?
Assign to Q_temp using signal assignment <= instead of variable assignment :=
Sensitivity lists for both your processes are incomplete
As #Morten mentions: the direction of Din_p should probably downto instead of to
Bonus (pet peeve): don't use IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED, because they are not properly standardized. Use ieee.numeric_std instead.
i'm coding a 4-bit binary adder with accumulator:
library ieee;
use ieee.std_logic_1164.all;
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout bit;
done:out bit);
end binadder;
architecture binadder of binadder is
signal state: integer range 0 to 3;
signal sum,cin:bit;
begin
sum<= (x(0) xor y(0)) xor cin;
co<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
process
begin
wait until clk='0';
case state is
when 0=>
if(n='1') then
state<=1;
end if;
when 1|2|3=>
if(sh='1') then
x<= sum & x(3 downto 1);
y<= y(0) & y(3 downto 1);
cin<=co;
end if;
if(state=3) then
state<=0;
end if;
end case;
end process;
done<='1' when state=3 else '0';
end binadder;
The output :
-- Compiling architecture binadder of binadder
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):
No feasible entries for infix operator
"xor".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):
Type error resolving infix expression
"xor" as type std.standard.bit.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
No feasible entries for infix operator
"and".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in right operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
No feasible entries for infix operator
"and".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in left operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in right operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Type error resolving infix expression
"or" as type std.standard.bit.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):
No feasible entries for infix operator
"&".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):
Type error resolving infix expression
"&" as type
ieee.std_logic_1164.std_logic_vector.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(39):
VHDL Compiler exiting
I believe i'm not handling std_logic_vector's correctly. Please tell me how? :(
One of the features of VHDL is that very little functionality is provided in the base language itself. Most of it is provided by using packages. The second line of your code is an example of this (use ieee.std_logic_1164.all). This means that you are using all of the std_logic_1164 package. See here for what this package defines.
When you write code, you generally want to store your signals in either std_logic or std_logic_vector. There are two reasons for this. The first is that a std_logic can also represent values other than '0' or '1'. It can also represent 'Z' or 'X' for example. The second is that the simulators (such as modelsim that you are using) are optimised to run faster with std_logic.
As a general convention, it is good practice to always make the inputs and outputs from your entity a std_logic or std_logic_vector.
The specific problem you are having is that you are using the type bit (which is one of the very few types defined in the VHDL standard) with xor.
The simplest solution is to change the co output in your entity to be of type std_logic and to change the declaration for sum and cin to be of type std_logic.
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout std_logic;
done:out bit);
end binadder;
signal sum,cin:std_logic;
A further comment is that it is generally bad practice to make your ports inout unless you have a very good reason to do so as this removes some of the strict type checking that is built into the language. The best solution is to create a signal within the entity itself and assign the signal directly to the output.
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:out std_logic;
done:out bit);
end binadder;
signal co_int:std_logic;
begin
co_int<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
co <= co_int;
One final comment is that once the value of state is 1, how will it ever become 2 or 3?
Take a look into your logical-physical library mappings.
Check that the physical library actually has the packages dumped.
Make sure you are not using a different version of pre-compiled header with a different version of the simulator.
If nothing works, just make a local copy of ieee, compile the std_logic_1164 packages into it, move to work library and then compile your design. This has to work.