Hello I'm new at modelsim and I don't know how to use it properly and I it pops me this error.
near "S1": (vcom-1576) expecting BEGIN.
---CODE---
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity test_mux is
end test_mux;
architecture test_b of test_mux is
signal A1, B1: std_logic_vector(2 downto 0);
S1: std_logic;
D1: std_logic_vector(2 downto 0);
component mux_double_2to1 port (a, b, s: in bit; d: out bit);
end component;
begin
M1: mux_double_2to1 PORT MAP (a=>A1,b=>B1,s=>S1,d=>D1);
process
begin
A1 <= '001';B1 <= '010';S1 <= '0'; wait for 20 ps;
A1 <= '010';B1 <= '100';S1 <= '0'; wait for 20 ps;
A1 <= '111';B1 <= '011';S1 <= '0'; wait for 20 ps;
A1 <= '101';B1 <= '111';S1 <= '0'; wait for 20 ps;
A1 <= '010';B1 <= '001';S1 <= '1'; wait for 20 ps;
A1 <= '000';B1 <= '101';S1 <= '1'; wait for 20 ps;
A1 <= '101';B1 <= '010';S1 <= '1'; wait for 20 ps;
A1 <= '111';B1 <= '101';S1 <= '1'; wait for 20 ps;
end process;
end test_b;
---ENTITY---
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity mux_double_2to1 is port(
a, b: in std_logic_vector(2 downto 0);
s: in std_logic;
d: out std_logic_vector(2 downto 0));
end mux_double_2to1;
Also entity is compiled sucessfully. What should I do about that? Can anyone help me?
Hello someone from my school help me to fix my issue so here is the complete solution.
Thanks whoever tried to help me. I appreciate it
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity test_mux is
end test_mux;
architecture test_b of test_mux is
signal A1, B1, D1: std_logic_vector(2 downto 0);
signal S1: std_logic;
component mux_double_2to1 port (a, b, d: in std_logic_vector(2 downto 0); s: out std_logic);
end component;
begin
M1: mux_double_2to1 PORT MAP (a=>A1,b=>B1,s=>S1,d=>D1);
process
begin
A1 <= "001";B1 <= "010";S1 <= '0'; wait for 20 ps;
A1 <= "010";B1 <= "100";S1 <= '0'; wait for 20 ps;
A1 <= "111";B1 <= "011";S1 <= '0'; wait for 20 ps;
A1 <= "101";B1 <= "111";S1 <= '0'; wait for 20 ps;
A1 <= "010";B1 <= "001";S1 <= '1'; wait for 20 ps;
A1 <= "000";B1 <= "101";S1 <= '1'; wait for 20 ps;
A1 <= "101";B1 <= "010";S1 <= '1'; wait for 20 ps;
A1 <= "111";B1 <= "101";S1 <= '1'; wait for 20 ps;
end process;
end test_b;
Related
I am trying to show simulation results for a simple And or Invert circuit. I have been struggling to get to the bottom of this for a while now. The code compiles correctly although the simulation does not show the results I expected. The output signal shows as undefined for 5ns then shows a correct signal while the internal signals stated in my design do not show up at all during simulation.
Can anyone check my code for me? Thanks.
Design
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AOI is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
F : out STD_LOGIC);
end AOI;
architecture V1 of AOI is
begin
F <= (A and B) nor (C and D);
end V1;
architecture V3 of AOI is
signal I1, I2, I3 : std_logic;
begin
F <= not I3 after 1 ns;
I3 <= I1 or I2 after 2 ns;
I1 <= A and B after 2 ns;
I2 <= C and D after 2 ns;
end V3;
Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity andorinvertTB is
end;
architecture TB1 of andorinvertTB is
component AOI_component
port(A,B,C,D : in std_logic;
F : out std_logic);
end component;
signal A,B,C,D,F : std_logic;
for G1: AOI_component use entity work.AOI(V3);
begin
stimuli: process
begin
A <= '0'; B <= '0'; C <= '0'; D <= '0'; wait for 10 NS;
A <= '0'; B <= '1'; C <= '0'; D <= '1'; wait for 10 NS;
A <= '1'; B <= '0'; C <= '1'; D <= '0'; wait for 10 NS;
A <= '1'; B <= '1'; C <= '1'; D <= '1'; wait for 10 NS;
wait;
end process;
G1: AOI_component port map ( A=>A, B=>B, C=>C, D=>D, F=>F );
end;
Image of simulation results - Output F undefined at the start and missing internal singals I1, I2 and I3
i tried to compile the following VHDL code but i got an error message:
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
ENTITY testdoublemux IS
END testdoublemux;
ARCHITECTURE test_doublemux OF testdoublemux IS
SIGNAL A1,B1,D1 : std_logic_vector(2 downto 0); S1 : std_logic;
COMPONENT mux_double_2to1 port ( a,b: in std_logic_vector(2 downto 0); s : in std_logic; d : out std_logic_vector(2 downto 0) );
END COMPONENT;
BEGIN
M1: mux_double_2to1 PORT MAP ( a => A1 , b => B1 , s => S1 , d => D1 );
PROCESS
BEGIN
A1 <= '001'; B1 <= '010'; S1 <= '0'; wait for 20ps;
A1 <= '010'; B1 <= '100'; S1 <= '0'; wait for 20ps;
A1 <= '111'; B1 <= '011'; S1 <= '0'; wait for 20ps;
A1 <= '101'; B1 <= '111'; S1 <= '0'; wait for 20ps;
A1 <= '010'; B1 <= '001'; S1 <= '1'; wait for 20ps;
A1 <= '000'; B1 <= '101'; S1 <= '1'; wait for 20ps;
A1 <= '101'; B1 <= '010'; S1 <= '1'; wait for 20ps;
A1 <= '111'; B1 <= '101'; S1 <= '1'; wait for 20ps;
END PROCESS;
END test_doublemux;
The error message is:
** Error: D:\apps\modelsim starter edition\modelsim workspace\mux_doubletb.vhd(8): near "S1": (vcom-1576) expecting BEGIN.
The entity code is:
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
ENTITY mux_double_2to1 is
PORT
(a, b: in std_logic_vector(2 downto 0);
s: in std_logic;
d: out std_logic_vector(2 downto 0)
);
END mux_double_2to1;
ARCHITECTURE dataflow3 OF mux_double_2to1 IS
BEGIN
d <= a WHEN s='0' ELSE b;
END dataflow3;
I'm working on an ALU using a certain set of functions. I figured that the addition and bitshift portions would be a lot easier if I used an extra bit to store the carry out. I'm trying to concatenate an extra bit to two 8 bit long 'std_logic_vector's. The extra bit would hold the carry out in the addition.
However when I go to run the simulation after some debugging it doesn't look like the lines I used to give s_a and s_b their values are doing anything. If I were to take out the default values they come out empty.
I'm sure the error is something silly, I'm not to familiar with how concatenation works in vhdl, maybe theres a better way of storing the carry out, any help would be appreciated.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity ALU is
Port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(3 downto 0);
Cin : in std_logic;
Result : out std_logic_vector(7 downto 0);
C : out std_logic;
Z : out std_logic);
end ALU;
architecture Behavioral of ALU is
signal s_result: unsigned(8 downto 0) := "000000000";
signal s_cin: unsigned(8 downto 0) := "000000000";
signal s_a: unsigned(8 downto 0) := "000000000";
signal s_b: unsigned(8 downto 0) := "000000000";
signal s_exempt: std_logic := '0';
begin
s1: process(A, B, SEL, CIN)
begin
s_a <= ('0' & unsigned(A));
s_b <= ('0' & unsigned(B));
s_cin(0) <= Cin;
s_exempt <= '0';
case SEL is
when "0000" =>
s_result <= s_a + s_b;
C <= s_result(8);
when "0001" => --ADDc Add with carry
s_result <= s_a + s_b + s_cin;
C <= s_result(8);
when "0010" => --SUB
if(s_a > s_b) then
s_result <= s_a - s_b;
C <= '0';
else
s_result <= s_b - s_a;
C <= '1';
end if;
when "0011" => --SUBc Subtract with carry
if(s_a > (s_b + s_cin)) then
s_result <= s_a - s_b - s_cin;
C <= '0';
else
s_result <= s_b - s_a - s_cin;
C <= '1';
end if;
when "0100" => --CMP Compare both values
if(s_a > s_b) then
C <= '0';
Z <= '0';
elsif(s_a = s_b) then
Z <= '1';
C <= '0';
else
C <= '1';
Z <= '1';
end if;
s_exempt <= '1';
when "0101" => --AND
s_result <= s_a AND s_b;
C <= '0';
when "0110" => Z<= '1'; --OR
s_result <= s_a OR s_b;
C <= '0';
when "0111" => --EXOR
s_result <= s_a XOR s_b;
C <= '0';
when "1000" => --TEST, comparator, flag change ONLY
if((s_a AND s_b) = "000000000")
then
C <= '0';
Z <= '1';
else
C <= '0';
Z <= '0';
end if;
when "1001" => --LSL Left shift
s_result <= s_a sll 1;
C <= s_result(8);
when "1010" => --LSR RIght shift
C <= s_a(0);
s_result <= s_a srl 1;
when "1011" => Z<= '1'; --ROL Rotate Left
s_result <= s_a sll 1;
C <= s_result(8);
s_result(0) <= s_result(8);
when "1100" => Z<= '1'; --ROR Rotate Right
C <= s_a(0);
s_result <= s_a srl 1;
s_result(0) <= s_a(0);
when "1101" => --ASR Arithemetic Roation
C <= s_a(0);
s_result <= s_a srl 1;
s_result(8) <= s_a(7);
when "1110" => --MOV Moves data into result
s_result <= s_b;
s_exempt <= '1';
when others =>
s_result <= "000000000";
s_exempt <= '1';
Z <= '0';
C <= '0';
end case;
if(s_exempt = '0') -- Checks Result for 0 if hasn't been found
then
if(s_result(7 downto 0) = "00000000")
then
Z <= '1';
else Z <= '0';
end if;
end if;
Result <= std_logic_vector(s_result(7 downto 0));
end process;
end Behavioral;
TESTBENCH:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity simulation is
end simulation;
architecture Behavioral of simulation is
COMPONENT ALU
Port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(3 downto 0);
Cin : in std_logic;
Result : out std_logic_vector(7 downto 0);
C : out std_logic;
Z : out std_logic
);
END COMPONENT;
signal A : std_logic_vector(7 downto 0) := "00000000";
signal B : std_logic_vector(7 downto 0) := "00000000";
signal SEL : std_logic_vector(3 downto 0) := "0000";
signal Cin : std_logic;
signal Result : std_logic_vector(7 downto 0) := "00000000";
signal C: std_logic := '0';
signal Z: std_logic := '0';
begin
uut: ALU PORT MAP (
A => A,
B => B,
SEL => SEL,
Cin => Cin,
Result => Result,
C => C,
Z => Z
);
stim_proc: process
begin
A <= "00000001";
B <= "00100001";
SEL <= "0000";
Cin <= '1';
wait for 10ns;
wait;
end process;
end Behavioral;
Any signal assigned in a process in VHDL is not updated until the process suspends. So, for example, the value of s_result from this line:
s_result <= s_a + s_b + s_cin;
will not be updated by the time that this line is executed:
C <= s_result(8);
You need to find out about delta delays, then once you have, you will need to rewrite your code.
VHDL is a hardware description language. You are designing hardware, not writing software. For example, your initialisation of all your signals will not be implemented in hardware, meaning that your simulation may well behave differently to your hardware:
signal s_result: unsigned(8 downto 0) := "000000000";
signal s_cin: unsigned(8 downto 0) := "000000000";
signal s_a: unsigned(8 downto 0) := "000000000";
signal s_b: unsigned(8 downto 0) := "000000000";
signal s_exempt: std_logic := '0';
Here is the code I have written for a 16 bit adder - The results of this files should be compared with a adder written in functional format: A+B, so they should make sense. The files are uploaded here:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder_16 is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
s : out STD_LOGIC_VECTOR (15 downto 0));
end Full_Adder_16;
architecture Behavioral of Full_Adder_16 is
component Full_Adder
port(x, y, cin: in std_logic;
sum, cout: out std_logic);
end component;
type cinout is array (0 to 15) of std_logic;
signal c : cinout;
signal cout : STD_LOGIC;
begin
c(0) <= '0';
adding: for i in 15 downto 0 generate
leftmost: if i=15 generate
Full_Adder_15: Full_Adder port map (x => a(i), y => b(i), cin => c(i), sum => s(i), cout => cout);
end generate;
otherwise: if i/=15 generate
Full_Adder_x: Full_Adder port map (x => a(i), y => b(i), cin => c(i), sum => s(i), cout => c(i+1));
end generate;
end generate;
end Behavioral;
And here is the testbench:
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity Full_Adder_16_tb is
end;
architecture bench of Full_Adder_16_tb is
component Full_Adder_16
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
s : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal a: STD_LOGIC_VECTOR (15 downto 0);
signal b: STD_LOGIC_VECTOR (15 downto 0);
signal s: STD_LOGIC_VECTOR (15 downto 0);
begin
uut: Full_Adder_16 port map ( a => a,
b => b,
s => s );
stimulus: process
begin
-- Put initialisation code here
A <= "0100010010110000";
B <= "0001010111011110";
wait for 10 ns;
A <= "0011000011110111";
B <= "0100000101000001";
wait for 10 ns;
A <= "0000000000000001";
B <= "0010011000000111";
wait for 10 ns;
A <= "0011110010110011";
B <= "1000111101011110";
wait for 10 ns;
A <= "0010000100100001";
B <= "1111101000100111";
wait for 10 ns;
A <= "0001011100100011";
B <= "0101101101101101";
wait for 10 ns;
A <= "1011000110111001";
B <= "1001011001011111";
wait for 10 ns;
A <= "0000001011001010";
B <= "1000011011101011";
wait for 10 ns;
A <= "0011110110100000";
B <= "1100111000000010";
wait for 10 ns;
A <= "0100000111111000";
B <= "0001001111100101";
wait for 10 ns;
A <= "1011111001111100";
B <= "0100001101010111";
wait for 10 ns;
A <= "1111000110000001";
B <= "1010000100001110";
wait for 10 ns;
A <= "0111000111001011";
B <= "1011000111010100";
wait for 10 ns;
A <= "1011011101101010";
B <= "1100111100101110";
wait for 10 ns;
A <= "1111001001010111";
B <= "0110010000100001";
wait for 10 ns;
A <= "0111111101101100";
B <= "0111000100001111";
wait for 10 ns;
A <= "0000111101111000";
B <= "1100011111101100";
wait for 10 ns;
A <= "0011100001100111";
B <= "1010101100100000";
wait for 10 ns;
A <= "1111111101000111";
B <= "0110111101011100";
wait for 10 ns;
A <= "0011111101000001";
B <= "1100100001100100";
wait for 10 ns;
A <= "1011011111000111";
B <= "1000111101011011";
wait for 10 ns;
A <= "1001011010010100";
B <= "0110001100101111";
wait for 10 ns;
A <= "1111111000100101";
B <= "1111111110001010";
wait for 10 ns;
A <= "1011100101000001";
B <= "0000100000000011";
-- Put test bench stimulus code here
wait;
end process;
end;
I just need the sum value since the result will be an alu output. But the result is wrong for some numbers, here is the wave form:
I have used the same adder to write a code for a multiplier but it works fine. Any comments to solve this problem will be appreciated.
The Full_adder is as follows:
library IEEE;
use IEEE.std_logic_1164.all;
entity Full_Adder is
port(x, y, cin: in std_logic;
sum, cout: out std_logic);
end Full_Adder;
architecture my_dataflow of Full_Adder is
begin
sum <= (x xor y) xor cin;
cout <= (x and y) or (x and cin) or (y and cin);
end my_dataflow;
I have been trying to make a generic sequence detector. When i try to simulate my design, I get a simulator 45-1 Fatal run time error. Can somebody please help me with this. Here is my Test bench and design.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Sequence_tb is
end Sequence_tb;
architecture Behavioral of Sequence_tb is
component sequence is
Generic(width: integer;
sequence: std_logic_vector);
Port(din,CLK,RST:in std_logic;
dout: out std_logic;
temp: buffer std_logic_vector(0 to width-1));
end component;
constant CLK_period: time := 10ns;
constant width: integer := 4;
constant sequence0: std_logic_vector(width-1 downto 0) := "1010";
signal din,CLK,RST,dout: std_logic := '0';
signal temp : std_logic_vector(0 to width-1) := (others=>'0');
begin
uut: sequence generic map(width=>width,sequence=>sequence0)
port map(din=>din,CLK=>CLK,RST=>RST,dout=>dout,temp=>temp);
CLK_proc: process
begin
CLK <= not CLK;
wait for CLK_period;
end process;
RST_proc: process
begin
RST <= '1';
wait for 20 ns;
RST <= '0';
wait;
end process;
din_proc: process
begin
din <= '1';
wait for 30 ns;
din <= '0';
wait for 10 ns;
din <= '1';
wait for 10 ns;
din <= '0';
wait for 10 ns;
din <= '1';
wait for 10 ns;
wait;
end process;
end Behavioral;
Design File:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Sequence is
Generic(width: integer;
sequence: std_logic_vector);
Port (din, CLK, rst: in std_logic;
dout: out std_logic;
temp: buffer std_logic_vector(0 to width-1));
end Sequence;
architecture Beh of Sequence is
subtype statetype is integer range 0 to width-1;
signal prstate,nxstate: statetype := 0;
begin
process(RST,CLK)
begin
if RST='1' then
temp <= (others => '0');
nxstate <= 0;
elsif CLK'event and CLK='1' then
temp(prstate) <= din;
for k in prstate downto 0 loop
if temp(k downto 0) = sequence(k downto 0) then
nxstate <= k;
exit;
else temp <= temp(1 to width-1) & '0';
end if;
end loop;
end if;
prstate <= nxstate;
end process;
dout <= '1' when prstate = width-1 and din = sequence(sequence'left) else '0';
end Beh;