In the code below, the line: mem_reg[wr_cmd_addr[SEG_ADDR_WIDTH*n +: INT_ADDR_WIDTH]][i*8 +: 8] <= wr_cmd_data[SEG_DATA_WIDTH*n+i*8 +: 8];
The index "i" is an integer type. It is being synthesized right??
I was under the impression that integer variables are only used for simulations in the initial procedural block
Also, the BRAM reg [SEG_DATA_WIDTH-1:0] mem_reg[2**INT_ADDR_WIDTH-1:0]; is being synthesized the number of times the genvar variable "n" loops in the for loop? The multiple generated BRAMs mem_reg will have the same names? And they cannot be accessed separately by name with something like: mem_reg[n] right?
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* DMA parallel simple dual port RAM
*/
module dma_psdpram #
(
// RAM size
parameter SIZE = 4096,
// RAM segment count
parameter SEG_COUNT = 2,
// RAM segment data width
parameter SEG_DATA_WIDTH = 128,
// RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// RAM segment address width
parameter SEG_ADDR_WIDTH = $clog2(SIZE/(SEG_COUNT*SEG_BE_WIDTH)),
// Read data output pipeline stages
parameter PIPELINE = 2
)
(
input wire clk,
input wire rst,
/*
* Write port
*/
input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] wr_cmd_be,
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] wr_cmd_addr,
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] wr_cmd_data,
input wire [SEG_COUNT-1:0] wr_cmd_valid,
output wire [SEG_COUNT-1:0] wr_cmd_ready,
output wire [SEG_COUNT-1:0] wr_done,
/*
* Read port
*/
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] rd_cmd_addr,
input wire [SEG_COUNT-1:0] rd_cmd_valid,
output wire [SEG_COUNT-1:0] rd_cmd_ready,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rd_resp_data,
output wire [SEG_COUNT-1:0] rd_resp_valid,
input wire [SEG_COUNT-1:0] rd_resp_ready
);
parameter INT_ADDR_WIDTH = $clog2(SIZE/(SEG_COUNT*SEG_BE_WIDTH));
// check configuration
initial begin
if (SEG_ADDR_WIDTH < INT_ADDR_WIDTH) begin
$error("Error: SEG_ADDR_WIDTH not sufficient for requested size (min %d for size %d) (instance %m)", INT_ADDR_WIDTH, SIZE);
$finish;
end
end
generate
genvar n;
for (n = 0; n < SEG_COUNT; n = n + 1) begin
(* ramstyle = "no_rw_check" *)
reg [SEG_DATA_WIDTH-1:0] mem_reg[2**INT_ADDR_WIDTH-1:0];
reg wr_done_reg = 1'b0;
reg [PIPELINE-1:0] rd_resp_valid_pipe_reg = 0;
reg [SEG_DATA_WIDTH-1:0] rd_resp_data_pipe_reg[PIPELINE-1:0];
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**INT_ADDR_WIDTH; i = i + 2**(INT_ADDR_WIDTH/2)) begin
for (j = i; j < i + 2**(INT_ADDR_WIDTH/2); j = j + 1) begin
mem_reg[j] = 0;
end
end
for (i = 0; i < PIPELINE; i = i + 1) begin
rd_resp_data_pipe_reg[i] = 0;
end
end
always #(posedge clk) begin
wr_done_reg <= 1'b0;
for (i = 0; i < SEG_BE_WIDTH; i = i + 1) begin
if (wr_cmd_valid[n] && wr_cmd_be[n*SEG_BE_WIDTH+i]) begin
mem_reg[wr_cmd_addr[SEG_ADDR_WIDTH*n +: INT_ADDR_WIDTH]][i*8 +: 8] <= wr_cmd_data[SEG_DATA_WIDTH*n+i*8 +: 8];
wr_done_reg <= 1'b1;
end
end
if (rst) begin
wr_done_reg <= 1'b0;
end
end
assign wr_cmd_ready[n] = 1'b1;
assign wr_done[n] = wr_done_reg;
always #(posedge clk) begin
if (rd_resp_ready[n]) begin
rd_resp_valid_pipe_reg[PIPELINE-1] <= 1'b0;
end
for (j = PIPELINE-1; j > 0; j = j - 1) begin
if (rd_resp_ready[n] || ((~rd_resp_valid_pipe_reg) >> j)) begin
rd_resp_valid_pipe_reg[j] <= rd_resp_valid_pipe_reg[j-1];
rd_resp_data_pipe_reg[j] <= rd_resp_data_pipe_reg[j-1];
rd_resp_valid_pipe_reg[j-1] <= 1'b0;
end
end
if (rd_cmd_valid[n] && rd_cmd_ready[n]) begin
rd_resp_valid_pipe_reg[0] <= 1'b1;
rd_resp_data_pipe_reg[0] <= mem_reg[rd_cmd_addr[SEG_ADDR_WIDTH*n +: INT_ADDR_WIDTH]];
end
if (rst) begin
rd_resp_valid_pipe_reg <= 0;
end
end
assign rd_cmd_ready[n] = rd_resp_ready[n] || ~rd_resp_valid_pipe_reg;
assign rd_resp_valid[n] = rd_resp_valid_pipe_reg[PIPELINE-1];
assign rd_resp_data[SEG_DATA_WIDTH*n +: SEG_DATA_WIDTH] = rd_resp_data_pipe_reg[PIPELINE-1];
end
endgenerate
endmodule
`resetall
try to use named blocks:
for (n = 0; n < SEG_COUNT; n = n + 1) begin : blkname
reg [SEG_DATA_WIDTH-1:0] mem_reg [2**INT_ADDR_WIDTH-1:0];
end
And access as:
assign x = blkname[i].mem_reg[j];
Main goal of this module is to generate output impuls on in random moment.
When I launch simulation module behave fine, but were i'm implementing it on board (BASYS 3) $urandom doesn't generate any numbers and my machine stay in SHOT state.
It is posible that $urandom works only in simulation but not on the board ?
My module looks like:
`timescale 1 ns / 1 ps
module random_shoot_gen
(
input wire pclk,
input wire rst,
output reg on
);
localparam COUNTER_LIMIT = 3000;
localparam IDLE = 2'b00;
localparam SHOT = 2'b01;
localparam WAIT = 2'b10;
reg [1:0] state = 0;
reg [1:0] state_nxt = 0; // machine start form IDLE satte
reg on_nxt = 0;
reg [25:0] counter = 0;
reg [25:0] counter_nxt = 0;
reg [25:0] s_time = 0;
reg [25:0] s_time_nxt = 0;
reg [6:0] rd = 0;
reg [6:0] rd_nxt = 0;
// ---------------------------------------
// state register
always #(posedge pclk) begin
state <= state_nxt;
on <= on_nxt;
counter <= counter_nxt;
rd <= $urandom%20;
s_time <= s_time_nxt;
end
// ---------------------------------------
// next state logic
always #(state or counter or s_time) begin
case(state)
IDLE:begin
if(counter >= COUNTER_LIMIT) begin
state_nxt = SHOT;
counter_nxt = 0;
end
else begin
state_nxt = IDLE;
counter_nxt = counter + 1;
end
end
SHOT:begin
counter_nxt = 0;
if (rd > 1)begin
state_nxt = WAIT;
end
else begin
state_nxt = IDLE;
end
end
WAIT:begin // to provide enaught widht on on signal
if(s_time >= 20) begin
state_nxt = IDLE;
s_time_nxt = 0;
end
else begin
state_nxt = WAIT;
s_time_nxt = s_time + 1;
end
end
endcase
end
always #* begin
case(state)
IDLE:
begin
on_nxt = 0;
end
SHOT:
begin
on_nxt = 0;
end
WAIT:
begin
on_nxt = 1;
end
endcase
end
endmodule
$urandom_range function is intended for test benches and cannot be used to model real hardware.
I suggest you use an LFSR to generate random numbers.
I am trying to determine how to turn this code into a 4-bit adder/subtractor using a fulladder. Right now it is doing the adding but I don't know how to do the subtract part.
module Adder #(parameter N = 4)(
output wire [N-1:0] sum, // sum
output wire co, // carry
input wire [N-1:0] x,
input wire [N-1:0] y,
input wire is_sub;
);
wire [N:0] c;
assign c[0] = 1'b0;
assign co = c[N];
genvar i;
generate
for (i = 0; i < N; i=i+1)
begin : counter_gen_label
FA FAInst (
.s(sum[i]),
.co(c[i+1]),
.a(x[i]),
.b(y[i]),
.cin(c[i]),
.is_sub(is_sub)
);
end
endgenerate
endmodule
module FA(
output reg s,
output reg co,
input wire a,
input wire b,
input wire cin,
input wire is_sub
);
always #(*)
begin
s = a ^ b ^ cin;
co = (a & b) | (a & cin) | (b & cin);
end
endmodule
How would I go by doing the subtraction inside the FA module?
Thanks!
FA does not need to use is_sub input.
Replace c[0] = 1'b0; with c[0] = is_sub;, and .b(y[i]) with .b(y[i] ^ is_sub).
This is from x - y = x + y' + 1 where y' means inverted y.
I have a design file ALU and another testbench. Here is my code:
parameter WIDHT = 4;
typedef enum logic[1:0] {
ADD =2'b00,
AND =2'b01,
OR = 2'b10,
XOR = 2'b11
} operation;
module ALU
(
input logic [WIDHT-1:0] A,B,
input operation op,
output logic [WIDHT-1:0] R,
output logic N,Z,V
);
always_comb
begin
unique case(op)
ADD: R = A+B;
AND: R = A&B;
OR: R = A|B;
XOR: R = A^B;
default : R=0;
endcase
if(R=='b0)
Z = 1;
else if (R[WIDHT-1] == 1'b1)
begin
if( A[WIDHT-1] == 1'b0 && B[WIDHT-1] == 1'b0)
V = 1;
else
N = 1;
end
else if (R[WIDHT-1] == 1'b0)
begin
if( A[WIDHT-1] == 1'b1 && B[WIDHT-1] == 1'b1)
V = 1;
else
begin
R=0;
Z=0;
V=0;
end
end
end
endmodule: ALU
Here is my testbench:
parameter W = 4;
module ALU_tb;
logic [W-1:0] A,B;
logic [1:0] op1;
logic [W-1:0] R;
logic N,Z,V;
ALU alu(A,B,op1,R,N,Z,V);
initial
begin
$monitor($time," A = %b, B = %b, ope = %b, R = %b, N = %b, Z = %b, V = %b",A,B,op1,R,N,Z,V);
A =0;
B=0;
#10;
for(A=0; A<2**W ; A++)
begin
for(B=0; B<'d2**W ; B++)
begin
/*for(op = op.first; op<=op.last; op.next)
#10; */
for(op1 = 2'b00; op1<=2'b11; op1++)
#10;
end
end
end
endmodule: ALU_tb
Now, the code compiles successfully but doesn't simulate. It gives me an error saying that I need to assign an enum to the same enum type or one of its value. What is that I am doing wrong? Any suggestions? One thing I found was to use packages and put the typedef enum in it and then import the package in both my design and testbench files. But I am trying to avoid using enum in my testbench. Can someone suggest something?
An enum is a stronger type than most integral types. You need use the package method to make the types assignment compatible.
Another option is making your port a bit-vector, and then casting it to operation type inside your design.
I'm studying Verilog and here's my first ALU.
I can't understand why the output does not display in the tester block.
Sample outputs(scroll horizontally):
FAIL: a=00010010000101010011010100100100, b=11000000100010010101111010000001, op=101, z=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz, expect=11010010100111010111111110100101
FAIL: a=10000100100001001101011000001001, b=10110001111100000101011001100011, op=101, z=zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz, expect=10110101111101001101011001101011
Why isn't z calculated?
ALU
module yAlu(z, ex, a, b, op);
input [31:0] a, b;
input [2:0] op;
output[31:0] z;
output ex;
wire [31:0] andRes, orRes, arithmRes, slt;
wire cout;
assign slt = 0; // not supported
assign ex = 0; // not supported
and myand[31:0] (andRes, a, b);
or myor[31:0](orRes, a, b);
//Instantiating yArith adder/subtractor from addSub.v
yArith addSub(arithmRes, cout, a, b, op[2]);
//Instantiating 4-to-1 32-bit multiplexor from 4to1Mux.v
yMux4to1 multiplexor(z, andRes, orRes, arithmRes, slt, op[1:0]);
endmodule
MULTIPLEXORS:
// 1-bit 2 to 1 selector
module yMux1(z, a, b, c);
output z;
input a, b, c;
wire notC, upper, lower;
not my_not(notC, c);
and upperAnd(upper, a, notC);
and lowerAnd(lower, c, b);
or my_or(z, upper, lower);
endmodule
//--------------------------------------------
// n-bit 2 to 1 selector
module yMux(z, a, b, c);
parameter SIZE = 2;
output [SIZE-1:0] z;
input [SIZE-1:0] a, b;
input c;
yMux1 mine[SIZE-1:0] (z, a, b, c);
endmodule
//--------------------------------------------
// n-bit 4-to-1 multiplexor
module yMux4to1(z, a0, a1, a2, a3, c);
parameter SIZE = 32;
output [SIZE-1:0] z;
input [SIZE-1:0] a0, a1, a2, a3;
input [1:0] c;
wire [SIZE-1:0] zLo, zHi;
yMux #(.SIZE(32)) lo(zLo, a0, a1, c[0]);
yMux #(.SIZE(32)) hi(zLo, a2, a3, c[0]);
yMux #(.SIZE(32)) final(zLo, zLo, zHi, c[1]);
// c in array is important (see LabL4.v page)
endmodule
//----------------------------------------------
ADDER/SUBTRACTOR BLOCK:
// A simple 1-bit full adder
module yAdder1(z, cout, a, b, cin);
output z, cout;
input a, b, cin;
xor left_xor(tmp, a, b);
xor right_xor(z, cin, tmp);
and left_and(outL, a, b);
and right_and(outR, tmp, cin);
or my_or(cout, outR, outL);
endmodule
//----------------------------------------------
// 32-bit adder with 1 bit carry
module yAdder(z, cout, a, b, cin);
output [31:0] z;
output cout;
input [31:0] a, b;
input cin;
wire [31:0] in, out;
yAdder1 adder[31:0](z, out, a, b, in);
assign in[0] = cin;
assign in[1] = out[0];
assign in[2] = out[1];
assign in[3] = out[2];
assign in[4] = out[3];
assign in[5] = out[4];
assign in[6] = out[5];
assign in[7] = out[6];
assign in[8] = out[7];
assign in[9] = out[8];
assign in[10] = out[9];
assign in[11] = out[10];
assign in[12] = out[11];
assign in[13] = out[12];
assign in[14] = out[13];
assign in[15] = out[14];
assign in[16] = out[15];
assign in[17] = out[16];
assign in[18] = out[17];
assign in[19] = out[18];
assign in[20] = out[19];
assign in[21] = out[20];
assign in[22] = out[21];
assign in[23] = out[22];
assign in[24] = out[23];
assign in[25] = out[24];
assign in[26] = out[25];
assign in[27] = out[26];
assign in[28] = out[27];
assign in[29] = out[28];
assign in[30] = out[29];
assign in[31] = out[30];
assign cout = out[31];
endmodule
//----------------------------------------------
// Arithmetic module. Adds if ctrl = 0, subtracts if ctrl = 1
module yArith(z, cout, a, b, ctrl);
output [31:0] z;
output cout;
input [31:0] a, b;
input ctrl;
wire [31:0] notB, tmp;
wire cin;
assign notB = ~b;
assign cin = ctrl;
yMux #(.SIZE(32)) mux(tmp, b, notB, ctrl);
yAdder adderSubtractor(z, cout, a, tmp, cin);
endmodule
//----------------------------------------------
TESTER:
module labL;
reg [31:0] a, b;
reg [31:0] expect;
reg [2:0] op;
wire ex;
wire[31:0] z;
reg ok, flag;
yAlu mine(z, ex, a, b, op);
initial
begin
repeat(10)
begin
a = $random;
b = $random;
op = 3'b101;
//flag = $value$plusargs("op=%d", op);
#10;
// ERROR CASE
if (op === 3'b011)
$display("Error!");
else if (op === 3'b111)
$display("Error!");
// ARITHM CASE
else if(op === 3'b010)
expect = a + b;
else if(op === 3'b110)
expect = a + ~b + 1;
// AND CASE
else if(op === 3'b000)
expect = a & b;
else if (op === 3'b100)
expect = a & b;
// OR CASE
else if (op === 3'b001)
expect = a | b;
else if (op === 3'b101)
expect = a | b;
// DONE WITH CASES;
#5;
if (expect === z)
$display("PASS: a=%b, b=%b, op=%b, z=%b", a, b, op, z, ex);
else
$display("FAIL: a=%b, b=%b, op=%b, z=%b, expect=%b", a, b, op, z, expect);
end
$finish;
end
endmodule
Your yMux4to1 does not drive the z output, so that's why you see 'zzz' as the output.
This means undriven/high-impedance.
You should be able to use a waveform viewer/simulator to trace your outputs (much better than using print statements).
You are getting a high-impedance signal out on Z. This means that your output Z is not driven. You should step through your design in simulation and put traces on your control signals and Z. Your IDE should support this. You most likely do not have the design wired up correctly so it's important to check your datapath and make sure all inputs/outputs are properly connected.