I'm trying to build an RX channel for QPSK modulated signals on GNU Radio. I'm on the first stage of my project so the signal I'm sending in the USRP N210 is a carrier signal centered at 2.206 GHz.
However when I'm trying to observe the signal on GNU Radio using a constellation sink bloc I see all the points of the constellation rotating in a circle (when there should only be one point since I'm sending a carrier signal).
Here is my GNU Radio Flowgraph:
Maybe there is something wrong with the parameters of my blocs of with my configuration of the USRP.
When using QPSK modulation, square constellation in receiver is achieved only after proper symbol timing and carrier phase and frequency compensation. In order to achieve single dot, when single harmonic signal is transmited, in receiver you need a decimator, that picks a single point. If there is phase difference between local oscilators of Tx and Rx the dot will be displaced, and if there is frequency difference the dot will rotate.
Related
I'm working on a guitar effects "pedal" using the NEXSYS A7 Board.
For this purpose, I've purchased the I2S2 PMOD and successfully got it up and running using the example code provided by Digilent.
Currently, the design is a "pass-through", meaning that audio comes into the FPGA and immediately out.
I'm wondering what would be the correct way to store the data, make some DSP on this data to create the effects, and then transmit the modified data back to the I2S2 PMOD.
Maybe it's unnecessary to store the data?
maybe I can pass it through an RTL block that's responsible for applying the effect and then simply transmit the modified data out?
Collated from comments and extended.
For a live performance pedal you don't want to store much data; usually 10s of ms or less. Start with something simple : store 50 or 100ms of data in a ring (read old data, store new data, inc address modulo memory size). Output = Newdata = ( incoming sample * 0.n + olddata * (1 - 0.n)) for variable n. Very crude reverb or echo.
Yes, ring = ring buffer FIFO. And you'll see my description is a very crude implementation of a ring buffer FIFO.
Now extend it to separate read and write pointers. Now read and write at different, harmonically related rates ... you have a pitch changer. With glitches when the pointers cross.
Think of ways to hide the glitches, and soon you'll be able to make the crappy noises Autotune adds to most all modern music from that bloody Cher song onwards. (This takes serious DSP : something called interpolating filters is probably the simplest way. Live with the glitches for now)
btw if I'm interested in a distortion effect, can it be accomplished by simply multiplying the incoming data by a constant?
Multiplying by a constant is ... gain.
Multiplying a signal by itself is squaring it ... aka second harmonic distortion or 2HD (which produces components on the octave of each tone in the input).
Multiplying a signal by the 2HD is cubing it ... aka 3HD, producing components a perfect fifth above the octave.
Multiplying the 2HD by the 2HD is the fourth power ... aka 4HD, producing components 2 octaves higher, or a perfect fourth above that fifth.
Multiply the 4HD by the signal to produce 5HD ... and so on to probably the 7th. Also note that these components will decrease dramatically in level; you probably want to add gain beyond 2HD, multiply by 4 (= shift left 2 bits) as a starting point, and increase or decrease as desired.
Now multiply each of these by a variable gain and mix them (mixing is simple addition) to add as many distortion components you want as loud as you want ... don't forget to add in the original signal!
There are other approaches to adding distortion. Try simply saturating all signals above 0.25 to 0.25, and all signals below -0.25 to -0.25, aka clipping. Sounds nasty but mix a bit of this into the above, for a buzz.
Learn how to make white noise (pseudo-random number, usually from a LFSR).
Multiply this by the input signal, and mix or match with the above, for some fuzz.
Learn digital filtering (low pass, high pass, band pass for EQ), and how to control filters with noise or the input signal, the world of sound is open to you.
This is an architectural question regarding gnuradio(-companion) and since I am not sure how to tackle this problem in the first place I first describe what I want to achieve and then how I think I would to it.
Problem
I implement a special form of an RFID reader with an Ettus X310 SDR: The transmitter sends an OOK/AM modulated (PIE encoded) request, followed by a pure Sine wave. The RFID tag backscatters its response onto this sine wave using OOK/AM modulation in FM0 or "Miller subcarrier" coding (a form of a differential Manchester coding). I want to receive its response, translate it into bits (and form a PDU), buffer different responses in a FIFO and send them for further processing. The properties of the tag response are:
It is asynchronuous. I do not know when the response is coming and if it does, when the proper sampling times are: I cannot simply filter, sample, decimate the signal and use a simple slicer because I do not know what the sample points are.
The response comes into very small "bursts" (say, 100 bits). Hence I cannot afford performing timing recovery on bits and waste them (except I buffer the entire signal somehow which I do not think is the way to do it).
The signal starts with a small preamble (UHF RFID Gen2 preamble) which is 6 bits (~8 bit transitions). This may not be enough for for time recovery but can be used to identify the start of a response somehow.
It uses mentioned FM0 encoding, so I have a guaranteed transition every bit. For that reason, I do not have to sample them but could detect the transitions and convert them into bits. I would not need conventional clock recovery (e.g. M&M) either.
My Thoughts
"Ordinary" gnuradio preprocessing brings me to the received oversampled bits: Downconversion, filtering; possibly a slicer which uses a lowpass filter to subtract the mean value and a comparator (note that even this may be challenging because the lowpass filter may have a large settling time of few bits until it obtains the right mean value).
In order to detect the actual transmission, I do not think I have much choice other than a simple squelch that detects a higher signal level than the noise floor (is this true or is there a way to detect the transmission using the preamble only?)
Once the squelch block detects a transmission, I could use a differentiator (or similar) to get the edges. But my understanding of the transition between this "baseband land" and "bits/PDUs" ends: I would need a block that triggers asynchronously (rather than samples at fixed intervals). In an actual system, the edges from the described detector could act as clock input of a flip flop. However, I do not see which standard gnuradio block would allow me to do this.
Once in "bits land", the bits (or PDUs) would be processed at a much lower rate. However, two clock domains are crossed: the normal baseband sampling rate, an irregular rate by which the transitions are detected and the rate at which the bits are read. For that reason, I would be looking for a FIFO or shift register, in which the detected bits are shifted in at whichever edge transition rate they come in and read out at the regular bit rate on the other side.
Question
What is the correct architecture/approach to implement this in gnuradio?
I could imagine to implement this with my own blocks. But as much as possible I would like to use standard block, gnuradio-companion. I would like to resort to own blocks (in particular C++) only as last resort if either not possible otherwise or if it would really not be the right way to so it otherwise.
I would like to recover the real waveform of a filtered signal.
A shunt is dedicated for the current sensing (fast transient). This shunt is connected to a coaxial cable (1m). This coaxial cable is connected to the input of the oscilloscope.
We can model this cable a LC filter (low pass filter), R is very low. The cutoff frequency is around 2MHz.
The signal acquired (Excel file) in the oscilloscope presents some ringing due to the LC filter response.
Indeed we have:
v(n)= i(n)*h(t)
i(n) is the sequence of the current wave
h(t) is the transfer function of my filter (LC)
* represents the convolution operator
Let’s compute the fft of each signal:
V(k)=I(k).H(k)
Then
I(k)=V(k)/H(k)
To recover i(n) I have to compute the IFFT of V(k)/H(k)
Therefore:
i(n)= Real ( IFFT (V(k)/H(k)))
Is it the right way to process to recover the unfiltered waveform?
Do I miss something?
Thanks in advance for your help!
I can share the file later.
In theory is correct. In practice, you might want to obtain the real response of your cable (filter). You can use any calibration method (i.e. single tone, harmonics, etc). This might prove challenging depending on your equipment due to the high frequency response expected from the coax cable.
Another issue that you might face is that you will hit the noise floor of the system. In ideal math, you would not have such noise, but in real instrumentation, your signal is more like:
v(n) = (i(n) + Noise_i(n) * h(n)) + SystemNoise(n)
Therefore, the fourier transfroms will be biased due to the noise floor of the instrumentation. This will reflect in the inverse transforms and will not reconstruct your signal completely. The more noise you have in the system, the less accurate your reconstruction will be.
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System timer
Computers contain a timer containing programmable channels. Programmable
channels mean timers of different durations. How to design such a circuit with four
programmable channels, each disabled initially. An enable input, two channel select
inputs and 4 lines for duration input can set any channel to a given duration from 1-
15. Zero means to disable a channel. Four output lines correspond to the channels and
are set high as soon as the corresponding timer expires.
Inputs
Clock Pulse CP
Input Available IA
Channel Select CS0, CS1
Duration D0…D3
Outputs
Timer Expire : TA, TB, TC, TD
I want to use Discrete logic ICs like Flip-Flops,Logic Gates,Decoders,Multiplexers,Encoders, etc.Data input is to be done using buttons(Push-buttons) and output should be displayed on LEDs. The clock should be common.
Single shot Timer consists of:
n-bit binary counter
driven by the input clock source CP and reseted by start input. With each clock pulse increments its value. The reset input should be hooked up to the timer start signal.
n-bit LATCH register
to store the timer Interval value (your per channel duration D0..D3)
n-bit comparator
to compare counted value and the Interval value. The XOR of equal bits is zero so if you or all xored bits together the result is 0 if both LATCH register value and Counter value are the same.
output flip flop
to remember expiration of timer (for non pulse mode operation) the output is your TA.TB,TC,TD The start impulse should also reset the RS on circuit I do this by WR but I suspect you will have Start signal separately instead...
Something like this:
You need to take into account the negations and auxiliary inputs of used ICs to make it work properly (some has negated WR some not ... the same goes for all pins so always check datasheet). So do not forget to add the chip selects and output enables signals to their working conditions.
multi channel timer
Well you just add the LATCH and comparators for each channel each connected to the same counter. The tricky part is the channel selection and starting part. you need to add decoder 1 from 4 to select the correct LATCH while setting the D0..D3. To draw a circuit for that part I would need to know more about the purpose of this ... Also if you set the Intervals only manually then you can use DIP switches instead the LATCH and the selection circuitry making it all much simpler.
All of above can be made just from NAND or NAND gates instead of concrete IC implementation. For that you need to use Karnaugh Maps and Boolean algebra.
It is a while I done something with raw gates as now is much easier cheaper faster to use MCU/FPGA for all of this so beware I could have miss something trivial (like negation gate somewhere)... anyway even then this should got the idea behind timers
BTW C++ representation of this is:
int cnt=0,D=?;
bool TA=0;
for (;;)
{
if (cnt==D) TA=1;
cnt=(cnt+1)&15;
}
[Edit1] the 4 channels version
This is based on the above text. There is also another option with less components that use 4 nibble RAM module instead of LATCH registers and decoder composing of single timer continuously looping through all channels by 4 x times CP multiplied clock (for example by XORing delayed CP signals).
I need to use keyboard as input for musical notes, and digilent speaker as output.
I plan to use only one octave.
My most intriguing questions are:
How do I represent the musical notes in VHDL code.
How do I (or do I need to) implement a DAC module that uses Spartan 3E Starter's built-in DAC? I have read on other forums that it can't be implemented. I need to use it in order to transmit the note to the speaker. The teacher who supervises my and my colleagues' projects suggested me to look into PWM for that(but all I've found is explained in electronic manner, no accompanying code, or explanation on implementation).
Besides keyboard controller, a processing module(for returning the note corresponding to the pressed key from the notes vector) and DAC, that I have figured out so far that I need, what else do I need.
There is a DAC (see comments)
There is no DAC on the Spartan-3E Starter Kit. Using a low-pass PWM signal is a common way to generate analog signal level from digital output.
You need to define a precision for your PWM, let's say 8 bits or 256 levels. For each audio sample you want to output, you need to count from 0 to 255. When the counter is less than the desired sample level, output 1, otherwise output 0. When the counter reach 255, reset it and go to the next sample.
Thus, if you want 8 bits precision (256 levels) and 8KHz signal, the counter will have to run at 256*8000 = 2.048MHz.
For your other questions, there is no easy answer. It's your job, as designer, to figure that out.