I am able to successfully analyze and run a simple VHDL counter in GHDL on macos, but when launching GTKW, the use of a generic causes problems.
The error message is
Unable to block on application (GetProcessPID() returned 184467095516)
Any ideas what this means or what gives rise to this error? (Couldn't find anything Googling it)
It seems to be connected to this line
signal count: unsigned (G_NBITS-1 downto 0)
From this code segment
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_simple is
generic(
G_NBITS : integer range 1 to 32 := 3
);
port(
clk : in std_logic;
reset_n : in std_logic;
--count_out : out std_logic_vector(G_NBITS-1 downto 0)
count_out : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of counter_simple is
--signal count: unsigned (G_NBITS-1 downto 0)
-- ABOVE LINE CRASHES gtkwave
-- Unable to block on application (GetProcessPID() returned 184467095516)
-- so instead:
signal count: unsigned (2 downto 0);
begin
counting : process (clk, reset_n)
begin
if (reset_n = '0') then
count <= (others => '0');
elsif rising_edge(clk) then
count <= count +1;
end if;
end process;
--count_out <= std_logic_vector(count(G_NBITS-1 downto 0));
count_out <= std_logic_vector(count(2 downto 0));
end rtl;
Printing the counter with report, in a testbench (around this counter) is fine in both cases, i.e. in both cases the counter runs 0..7.
So the simulation runs but there appears to be something offensive in the .ghw file.
I haven't had much luck with answers here, but I did read-up on the .ghw file that is output by GHDL, and it is a custom format readable by GTKW.
I tried an alternative format, vcd, and that seems to be fine:
Instead of the default
ghdl -r counter_simple_tb --stop-time=10ns --wave=counter_simple.ghw
Use VCD
ghdl -r counter_simple_tb --stop-time=10ns --vcd=counter_simple.vcd
(Note: you have to use the --vcd switch. Filename extension alone is not enough)
As a workaround this will do.
Hopefully this helps others stuck on this too.
It's of course possible that all this has been fixed in the meantime, as the macos binary for GHDL (v 0.29, 32bit) is quite a few versions behind the latest (v 1.0)
$ ghdl -v
GHDL 0.29 (20100109) [Sokcho edition]
and I am running it on a 64bit machine.
Related
In my filter design , I am using fixed point arithmetic and using sfixed for signals. The design synthesizes with all timing met but my functional simulation and post synth/P&R simulation do not match after arith logic blocks.. Giving a small ex below, where I see that crf_int_r does not match in Post synth simulation.. Can someone help me understand , whether it is not synthesized properly or some other issue for a mismatch between functional and post synth simulation..Using Xilinx ISE 14.7 and VHDL 200X option in ISE.
signal add_alpha1_r : sfixed(5 downto -13) ;
signal add_alpha2_r : sfixed(6 downto -13) ;
signal crf_r : sfixed(17 downto -13) ;
signal crf_int_r : sfixed(17 downto -7) ;
signal alpha_log : sfixed(4 downto -13) ;
signal imgdel_r_d4 : sfixed(4 downto -13) ;
signal imgsum_d2 : sfixed(4 downto -13) ;
add_alpha1_r <= imgdel_r_d4 - imgsum_d2 ; --19.13
add_alpha2_r <= alpha_log + add_alpha1_r ; -- 20.13
crf_r <= add_alpha2_r * beta ; -- 31.13
crf_int_r <= crf_r(17 downto -7);
You encountered a synthesis bug. Making a Minimal, Complete, and Verifiable example from the code presented in the comments, I have tried to synthesize this with ISE 14.7 and VHDL-200X option on:
library ieee;
use ieee.std_logic_1164.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
entity sfixed_test is
port (alpha_log : out sfixed(4 downto -13));
end sfixed_test;
architecture rtl of sfixed_test is
constant alpha : sfixed(10 downto 0) := "00001111000"; -- 120
type rom_t is array(0 to 2047) of sfixed(4 downto -13);
constant alpha_rom : rom_t := (120 => "111111111111111111",
others => "000000000000000000");
begin -- rtl
alpha_log <= alpha_rom(to_integer(alpha));
end rtl;
XST reports the following warning:
Warning: "::fixed_pkg:TO_INTEGER (sfixed): metavalue detected, returning 0"
A quick look into the RTL or Technology Map Viewer shows, that all outputs were connected to ground instead of VCC as intended in my example.
The problem is the implementation of to_integer as described bewlow. You can work around this, if you change the reading from the ROM to:
alpha_log <= alpha_rom(to_integer(unsigned(std_logic_vector(alpha))));
and also include the package ieee.numeric_std. Then everything works fine.
Further notes: The warning message refers to line 5085 ff. of ieee_proposed/fixed_pkg_c.vhd shipped with ISE. It reads:
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
Is_X(arg) checks whether the argument contains a U, X, Z, W, or -. It fails here if arg (which is alpha) is a constant. But, it works when alpha is a signal (input).
I am trying to be multiply the values in the line:
Q<= unsigned(reg_output) or (unsigned(multiplicand) and unsigned(shifted_lsb)*"0010");
note: I know multiplicand is a std_logic_vector, I did this for comparison via the if's.
Everytime I compile I get the error:
Illegal type conversion from ieee.std_logic_1164.STD_LOGIC to ieee.NUMERIC_STD.UNSIGNED (non-numeric to array).
here is my code below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shiftaddr is
port(
clk, clear : in std_logic;
multiplicand: in std_logic_vector(3 downto 0);
reg_output: in unsigned(7 downto 0);
shifted_lsb: in std_logic;
Q: out unsigned(7 downto 0) );
end shiftaddr;
architecture arch of shiftaddr is
signal temp: std_logic_vector(3 downto 0);
begin
shift: process(clk,clear,multiplicand, shifted_lsb,reg_output) --Define a process and state the inputs
begin
if (clk = '0') then
Q <= reg_output;
end if;
if (clk = '1') then
if (multiplicand(0) = '1') then Q <= (reg_output);
end if;
if (multiplicand(1) = '1') then
Q<= unsigned(reg_output) or (unsigned(multiplicand) and unsigned(shifted_lsb)*"0010");
end if;
end if;
end process;
end arch;
How do I go about fixing this? Thanks
The problem comes from:
unsigned(shifted_lsb)*"0010"
shifted_lsb is not a vector, you cannot convert it to unsigned which is a vector type. As suggested by Khanh N. Dang you could just test its value instead.
But your code is probably bogus: your sensitivity list is not that of a synchronous process while one of your signals is named clk. Moreover, if you want your process to be a synchronous one you will have a problem because you are using both states of the clock. You should probably:
indent your code so that we can read it without too much effort,
think hardware first: if you have a clear idea of the hardware you want (registers, adders, multiplexers...), coding usually becomes very easy,
read again the part of your text book about synchronous processes.
I'm new to VHDL and I've just been messing around with Quartus II 9.0 and decided to make a register type component. I think my logic is right but I'm not getting any output when I run the simulation. I created a waveform to test possible situations (used node finder to list all inputs and output, generated the functional simulation netlist) but I do not get any output for Q. Not even the simple case when clr = 1 and all of Q should be set to 0.
library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY Register32 IS PORT (
d : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- input.
ld : IN STD_LOGIC; -- load/enable.
clr : IN STD_LOGIC; -- async. clear.
clk : IN STD_LOGIC; -- clock.
Q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); -- output.
END Register32;
ARCHITECTURE description OF Register32 IS
BEGIN
process (clk) begin
if (clr = '1') then
Q <= (others => '0');
else
if (rising_edge(clk)) then
if (ld = '1') then
Q <= d;
end if;
end if;
end if;
end process;
END description;
When the clr is asynchronous, then it must be included in the process
sensitivity list, since update of Q should react immediately on changes to
clr. Quartus II has probably given you a warning about this, if you dive
into the warnings.
The clr missing in the sensitivity list is not that visible if clk is
running, but if your current test bench only tries clr so far, it may be the
reason that you do not see any changes of Q.
This is a code for two 6 bit serial adder.It acts like a scoreboard.iam getting a compiling error " cannot read output q ".please help me out of this.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity board IS
port
(
C: in std_logic;
h : in std_logic_vector(5 downto 0);
q : out std_logic_vector(5 downto 0)
-- s,cout : out std_logic
);
end board;
architecture archi of board is
signal tmp: std_logic_vector(5 downto 0);
begin
process(C)
begin
if(C'event and C='1') then
tmp<= std_logic_vector (unsigned(q) + unsigned(h));
end if;
end process;
q<=tmp;
end archi;
For some reason (why?) you cannot read from output ports directly. Create an internal signal, e.g. q_i, replace all q by q_i and assign the internal signal to the output port, i.e. q <= q_i.
On a further note, your tmp signal is not necessary. You can write q_i <= std_logic_vector((unsigned(q_i) + unsigned(h)); in a clocked process.
You should be using numeric_std rather than std_logic_unsigned. std_logic_unsigned is not an official ieee supported package. At the top of your file do this and your problems should go away:
use ieee.numeric_std.all;
Also don't put signal h in your process sensitivity list. That process is a clocked process and you shouldn't have any signal but your clock and an asynchronous reset in the sensitivity list (if you're using an async reset). You don't need a reset at all here.
I have a piece of VHDL code that compile but when I try to synthesize it I get stuck, meaning the synthesization never ends and I have in the console:
Analyzing Entity Interpretor in library work (Architecture ).
I've tried to understand why but I can't. All I know is that if I comment the line CPT_PAN <= CPT_PAN - 1; then all of sudden I can synthesize.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Interpretor is
Port (SCAN_CODE : IN STD_LOGIC_VECTOR(7 downto 0));
end Interpretor;
architecture Behavioral of Interpretor is
Signal CPT_PAN : Integer range 0 to 255 := 0;
begin
process(SYS_CLK)
begin
if (SYS_CLK'EVENT and SYS_CLK = '1') then
if SCAN_CODE = "01101011" then
if CPT_PAN /= 0 then
CPT_PAN <= CPT_PAN - 1; -- Line to be commented to synthesize
end if;
end if;
end if;
end process;
end Behavioral;
Which synthesis tool? It would be useful to know.
Xilinx XST 14.3 simply reports <sys_clk> is not declared. and exits.
Add an input port for it, and it synthesises correctly, producing no hardware!
Add an output,
entity Interpretor is
Port (
SYS_CLK : in std_logic;
SCAN_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
Zero : Out Boolean
);
end Interpretor;
and a line to the architecture
Zero <= CPT_Pan = 0;
and it generates pretty much what you would expect. It still optimises away to nothing since CPT_Pan is initialised to 0, and that case is not handled at all by the process.
Dare I ask if you simulated this before trying to synthesise?