I am new to C++ programming and making MakeFiles, so straight to the point:
here is my MakeFile:
CC = g++
INCLUDES = -I\ include/
CFLAGS = -Wall \ -g\ $(INCLUDES)
LDFLAGS = -L./lib
main: main.o
$(CC) main.o $(LDFLAGS) -o main
main.o: src/main.cpp
$(CC) $(CFLAGS) -c src/main.cpp -o main.o
Sorry for noobness :( . my File structure:
src/
include/
Makefile
and "make" shows :
g++: error: -g -I include/: No such file or directory
Kindly please also give suggestions for improving this file
You dont require \ after every option
Please see below changes:
CC = g++
INCLUDES = include/
CFLAGS = -Wall -g -I$(INCLUDES)
LDFLAGS = -L./lib
main: main.o
$(CC) main.o $(LDFLAGS) -o main
main.o: src/main.cpp
$(CC) $(CFLAGS) -c src/main.cpp -o main.o
Related
I'm trying to move my Makefile to cmake. The problem is that when it comes to linking stage, it cannot find the shared library.
My cmake is:
set(PROJECT_LINK_LIBS libsr_tps.so)
link_directories(absolute/path/to/the/library)
I also tried:
find_library(PROJECT_LINK_LIBS NAMES sr_tps PATHS "${PROJECT_SOURCE_DIR}/lib")
and then:
add_executable(project ${SOURCE})
target_link_libraries(project ${PROJECT_LINK_LIBS})
The sources can be cross-compiled successfully. But after compiling, it always says:
/absolute/path/to/ld: cannot find -lsr_tps
collect2: ld returned 1 exit status
given that libsr_tps.so has already been pre-cross-compiled.
Makefile works fine for both compiling and generating the final executable.
I have been looking for the potential issue for many hours. The solutions just don't work.
What could be wrong?
Thanks.
Update:
The way for build with make:
Set some environment parameters, i.e. some export.
Makefile:
LDFLAGS += -L./lib
CFLAGS += -Wall -Wno-pointer-sign
LDLIBS = -lsr_tps
all: $(TARGET)
$(TARGET): $(OBJS) $(OBJS_ROS)
$(CC) $(LDFLAGS) $(OBJS) $(OBJS_ROS) $(LDLIBS) -o $(TARGET)
cp $^ ./$(BINARY)/$(OBJ_DIR)
mv $# ./$(BINARY)
.c.o: $(CC) $(CFLAGS) -o $# -c $<
Update 2:
Here is my Makefile:
TARGET = ros
LDFLAGS += -L./lib
CFLAGS += -Wall -Wno-pointer-sign -DWSU_5001 -I./include -I./include/WSU-5001_include -I./include/J2735 -I./ -pthread -O
LDLIBS = -lsr_tps -lrisapi -lrt -lipc -lm -ldot2 -ldot3 -lcrypto -lgps -ltpsapi
SHARED_FLAGS = -fPIC -shared
BINARY= bin
SRC_DIR = ./src
J2735_DIR = ./src/J2735
#OBJ_DIR = ./binary/obj
OBJ_DIR = obj
OBJS_TEST=${ASN_MODULE_SOURCES:.c=.o} ${ASN_CONVERTER_SOURCES:.c=.o}
OBJS=${ASN_MODULE_SOURCES:.c=.o}
OBJS_ROS = ros.o tx.o rx.o util.o config.o
all: $(TARGET)
mkdir -p $(BINARY)
mkdir -p $(BINARY)/$(OBJ_DIR)
$(TARGET): $(OBJS) $(OBJS_ROS)
$(CC) $(LDFLAGS) $(OBJS) $(OBJS_ROS) $(LDLIBS) -o $(TARGET)
cp $^ ./$(BINARY)/$(OBJ_DIR)
mv $# ./$(BINARY)
# $(TARGET): $(OBJS)
# $(CC) $(OBJS) $(CFLAGS) -o $#
.SUFFIXES:
.SUFFIXES: .c .o
.c.o:
$(CC) $(CFLAGS) -o $# -c $<
Command line after executing make:
path/to/powerpc-e300c3-linux-gnu-gcc -L./lib <all .o files> -lsr_tps -lrisapi -lrt -lipc -lm -ldot2 -ldot3 -lcrypto -lgps -ltpsapi -o ros
And below is my CMakeList:
cmake_minimum_required(VERSION 3.5.1)
project(Denso-ROS)
set(CMAKE_SYSTEM_NAME Denso-linux)
set(CMAKE_SYSTEM_PROCESSOR "^(powerpc|ppc)")
set(GCC_COVERAGE_COMPILE_FLAGS "-static -Wall -Wno-pointer-sign -DWSU_5001 -pthread -O")
#################
#problem
#set(GCC_COVERAGE_LINK_FLAGS "libsr_tps.so -lrisapi -lrt -lipc -lm -ldot2 -ldot3 -lcrypto -lgps -ltpsapi")
#set(GCC_COVERAGE_LINK_FLAGS "-L./lib")
#set(CMAKE_LINK_LIBRARY_FLAG "-lsr_tps -lrisapi -lrt -lipc -lm -ldot2 -ldot3 -lcrypto -lgps -ltpsapi")
#set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}" )
set(PROJECT_LINK_LIBS libsr_tps.so)
link_directories(home/yufeiyan/DENSO-WSU5K1-SDK_VM_Ubuntu_Peloton/Denso/lib)
#################
set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" )
set(tools ${PROJECT_SOURCE_DIR}/toolchain/bin)
set(CMAKE_C_COMPILER ${tools}/powerpc-e300c3-linux-gnu-gcc)
set(CMAKE_CXX_COMPILER ${tools}/powerpc-e300c3-linux-gnu-g++)
find_library(DENSO_LIB NAMES sr_tps PATHS "${PROJECT_SOURCE_DIR}/lib")
message(STATUS "${DENSO_LIB}")
include_directories(
${PROJECT_SOURCE_DIR}
include
include/J2735
include/WSU-5001_include)
file(GLOB SOURCE ${PROJECT_SOURCE_DIR}/*.c src/*.c src/J2735/*.c)
list(REMOVE_ITEM SOURCE ${PROJECT_SOURCE_DIR}/src/J2735/converter-example.c)
list(REMOVE_ITEM SOURCE ${PROJECT_SOURCE_DIR}/src/J2735/test.c)
#add_executable(ros ${SOURCE1} ${SOURCE2} ${SOURCE3})
add_executable(ros ${SOURCE})
target_link_libraries(ros ${PROJECT_LINK_LIBS})
Command line after executing make:
path/to/powerpc-e300c3-linux-gnu-gcc -static -Wall -Wno-pointer-sign -DWSU_5001 -pthread -O <all .o files> -L/path/to/project/lib -lsr_tps -Wl,-rpath, path/to/project/lib path/tp/powerpc-e300c3-linux-gnu/bin/ld: cannot find -lsr_tps
Many thanks to Tsyvarev.
Let me sum up the issue and solution:
The linker can not find the library due to the incorrect path. I used link_directories(absolute/path/to/lib), and it returned a duplicate path. Instead, using link_directories(${PROJECT_SOURCE_DIR}/lib) solved the problem. The linker has the correct path and find the library.
In the meantime, I remove the -static option for CFLAGS. This option may also cause the linker not finding the library.
I'm doing a Makefile to make objects with the same gcc command. This file looks like this:
SRCLIB = main.c srv.c
OBJLIB = main.o srv.o
CC = gcc
CCFLAGS = -Wall -Werror
$(OBJLIB) : $(SRCLIB)
$(CC) $(CCFLAGS) -c $^ -o $#
The objetive is to execute this like:
gcc -Wall -c read_line.c -o read_line.o
gcc -Wall -c client.c -o client.o
But I don't know how to do it, and everything I tested is not working. Is it even possible to do this in a Makefile?
Your makefile expands to this, after the variables are expanded:
main.o srv.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
In make, using multiple targets in explicit rules like this is the same as writing the rule multiple times, once for each target. So, this is the same as this:
main.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
srv.o : main.c srv.c
$(CC) $(CCFLAGS) -c $^ -o $#
This means that if either of the source files changes, BOTH object files will be recreated (since each object depends on both sources, not just their own source file).
Further, in your compile line you use the variable $^ which expands to all the prerequisites. So your compile lines will expand to:
gcc -Wall -Werror -c main.c srv.c -o main.o
gcc -Wall -Werror -c main.c srv.c -o srv.o
which is illegal: if you use -c with the -o option you can only compile one source file.
Make has built-in rules that already know how to compile files, so there's no need to write your own. You can just write this:
SRCLIB = main.c srv.c
OBJLIB = main.o srv.o
CC = gcc
CCFLAGS = -Wall -Werror
.PHONY: all
all: $(OBJLIB)
and that's all you need.
I have a simple makefile that I am using in bash to compile a C++ program and its associated .h files, not every .h file has a .cpp file associated with it. I wrote a makefile where each dependency was called out explicitly and the CFLAG macro was used for each specific dependency and it did compile with the -O3 flag and ran nearly 3 times faster. However, when I use this simpler, but somewhat more sophisticated makefile, it does not compile with the -O3 flag even though it is clearly included with the CFLAG macro. Can someone point out to me what I am missing, I would greatly appreciate it.
OBJS = main.o Output_Files.o Calendar.o Random_Number_Generator.o \
Algorithm.o Statistics.o
DEPS = Output_Files.h Calendar.h Random_Number_Generator.h Algorithm.h \
Statistics.h
CC=c++
CFLAGS=-c -Wall -O3
all: economics
%o: %.cpp $(DEPS)
$(CC) $(CFLAGS) $# $<
economics: $(OBJS)
$(CC) $(OBJS)
main.o: main.cpp Data_Parser.h PDF_and_CDF.h
$(CC) $(CFLAGS) main.cpp
The rule:
%o: %.cpp $(DEPS)
$(CC) $(CFLAGS) $# $<
should be written with an extra dot:
%.o: %.cpp $(DEPS)
$(CC) $(CFLAGS) $<
Also, you don't want $# in the command line, or (if you must have it) you need to prefix it with -o.
The makefile is not using the faulty rule but instead uses the default rule for building C++ object files, and that most probably doesn't use $(CFLAGS) but uses $(CXXFLAGS) instead.
CC is the macro for the C compiler, not the C++ compiler. Normally, that is CXX. Also, the rule to build economics actually creates a.out and not economics.
I'd prefer it if you wrote:
SRCS = main.cpp Output_Files.cpp Calendar.cpp Random_Number_Generator.cpp \
Algorithm.cpp Statistics.cpp
OBJS = ${SRCS:.cpp=.o}
…
economics: $(OBJS)
$(CC) -o $# $(OBJS)
Putting it all together gives this new.makefile:
SRCS = main.cpp Output_Files.cpp Calendar.cpp Random_Number_Generator.cpp \
Algorithm.cpp Statistics.cpp
OBJS = ${SRCS:.cpp=.o}
DEPS = Output_Files.h Calendar.h Random_Number_Generator.h Algorithm.h \
Statistics.h
CC = c++
CFLAGS = -c -Wall -O3
all: economics
%.o: %.cpp $(DEPS)
$(CC) $(CFLAGS) $<
economics: $(OBJS)
$(CC) -o $# $(OBJS)
main.o: main.cpp Data_Parser.h PDF_and_CDF.h
$(CC) $(CFLAGS) main.cpp
Running make -n with the old makefile
$ make -n -f old.makefile
c++ -c -Wall -O3 main.cpp
c++ -c -o Output_Files.o Output_Files.cpp
c++ -c -o Calendar.o Calendar.cpp
c++ -c -o Random_Number_Generator.o Random_Number_Generator.cpp
c++ -c -o Algorithm.o Algorithm.cpp
c++ -c -o Statistics.o Statistics.cpp
c++ -o economics main.o Output_Files.o Calendar.o Random_Number_Generator.o Algorithm.o Statistics.o
$
Running make -n with the new makefile
$ make -n -f new.makefile
c++ -c -Wall -O3 main.cpp
c++ -c -Wall -O3 Output_Files.cpp
c++ -c -Wall -O3 Calendar.cpp
c++ -c -Wall -O3 Random_Number_Generator.cpp
c++ -c -Wall -O3 Algorithm.cpp
c++ -c -Wall -O3 Statistics.cpp
c++ -o economics main.o Output_Files.o Calendar.o Random_Number_Generator.o Algorithm.o Statistics.o
$
This is still an abnormal way of writing the make rules on a number of grounds, one being the $(CC) vs $(CXX) change. Normally, the -c option is not included in $(CFLAGS) or $(CXXFLAGS). Normally, you include $(CFLAGS) or $(CXXFLAGS) in the link line too (because some of the flags might affect linking). Often, you need libraries and related flags in the linker line too.
This leads to a more orthodox naming convention:
SRCS = main.cpp Output_Files.cpp Calendar.cpp Random_Number_Generator.cpp \
Algorithm.cpp Statistics.cpp
OBJS = ${SRCS:.cpp=.o}
DEPS = Output_Files.h Calendar.h Random_Number_Generator.h Algorithm.h \
Statistics.h
CXX = c++
CXXFLAGS = -Wall -O3
LDFLAGS =
LDLIBS =
all: economics
%.o: %.cpp $(DEPS)
$(CXX) -c $(CXXFLAGS) $<
economics: $(OBJS)
$(CXX) -o $# $(CXXFLAGS) $(OBJS) $(LDFLAGS) $(LDLIBS)
main.o: main.cpp Data_Parser.h PDF_and_CDF.h
$(CXX) -c $(CXXFLAGS) main.cpp
I am using the following makefile to build my project:
CC = /usr/bin/g++
CFLAGS = -Wall -pedantic -std=c++0x
LDFLAGS =
OBJ = main.o pnmhandler.o pixmap.o color.o
pnm: $(OBJ)
$(CC) $(CFLAGS) -o pnm $(OBJ) $(LDFLAGS)
%.o: %.c
$(CC) $(CFLAGS) -c $<
As I run make I get the following error:
/usr/include/c++/4.9.1/bits/c++0x_warning.h:32:2: error: #error This
file requires compiler and library support for the ISO C++ 2011
standard. This support is currently experimental, and must be enabled
with the -std=c++11 or -std=gnu++11 compiler options.
As I can read from the following line, the CFLAGS are not properly included, but I have no idea what I am doing wrong:
g++ -c -o main.o main.cpp
Also tried -std=c++11 and -std=gnu++11, without any results. Any ideas?
If I run make -Bn, I get:
g++ -c -o main.o main.cpp
g++ -c -o pnmhandler.o pnmhandler.cpp
g++ -c -o pixmap.o pixmap.cpp
g++ -c -o color.o color.cpp
/usr/bin/g++ -Wall -pedantic -std=c++0x -o pnm main.o pnmhandler.o pixmap.o color.o
EDIT: Replacing the rule %.o: %.c with %.o: %.cpp fixes my problem.
The reason you see
g++ -c -o main.o main.cpp
is that Make is invoking its standard rule to create the object file:
%.o: %.cpp
# recipe to execute (built-in):
$(COMPILE.cpp) $(OUTPUT_OPTION) $<
The command expands to
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c -o $# $<
Instead of setting CC and CFLAGS in your makefile, you should set CXX and CXXFLAGS, which are meant for C++ rather than C. That allows the built-in rule above to work for you, and then you just need to make sure the right linker is used, e.g. with
pnm: LINK.o=$(LINK.cc)
pnm: $(OBJ)
You also don't need the %.o: %.c rule, as you have no C sources.
Complete Makefile:
CXX = /usr/bin/g++
CXXFLAGS = -Wall -pedantic -std=c++0x
OBJ = main.o pnmhandler.o pixmap.o color.o
pnm: LINK.o=$(LINK.cc)
pnm: $(OBJ)
clean::
$(RM) pnm
.PHONY: clean
I have made a makefile in order to compile my files:
CFLAGS = -O3 -Wall -I /usr/local/cuda/include/
NVCCFLAGS = -O3 -arch sm_20
LDFLAGS = -O3 -L/usr/local/cuda/lib64 -lcudart
EXE = runAPP
app.o:app.cu
$(NVCC) $(NVCCFLAGS) -c $< -o $(CPPFLAGS) $(LIB_PATH) $(LDFLAGS) $#
$(EXE): app.o
$(NVCC) $(NVCCFLAGS) $(CFLAGS) $(LDFLAGS) -o $# $(CPPFLAGS) $(LIB_PATH) app.o \
-lANN_char -lz
cp $# ../bin
But I got this problem:
app.cpp:26:26: error: cuda_runtime.h: No such file or directory
app.cpp:27:18: error: cuda.h: No such file or directory
This is how I include them in the app.cpp:
#include <cuda.h>
#include <cuda_runtime.h>
Why is this problem?
I search something on google, they said that the app.cpp must be always app.cu, is it true?
Thanks in advance.
If your makefile, you have:
CFLAGS = -O3 -Wall -I /usr/local/cuda/include/
NVCCFLAGS = -O3 -arch sm_20
LDFLAGS = -O3 -L/usr/local/cuda/lib64 -lcudart
EXE = runAPP
app.o:app.cu
$(NVCC) $(NVCCFLAGS) -c $< -o $(CPPFLAGS) $(LIB_PATH) $(LDFLAGS) $#
CPPFLAGS should be expanding to nothing; try changing it to CFLAGS, or change CFLAGS to CPPFLAGS.