Unfortunately I can't properly debug a code in Modelsim. In fact, during the simulation the DUT is not displayed in the SIM panel (I am attaching a screenshot). So I can just see the waveforms generated by the testbench, but I cannot view the internal signals. It seems that for some reason the TESTER and the DUT are not connected.
You can add all the signals recursively with the following command:
add wave -recursive /*
Now, if you're not seeing the DUT, you may want to check the waring when the simulation is loading.
Do you see unbound warnings?
Did you compile your DUT file?
Do you find it in the library ?
Sébastien.
Related
I am writing a code for spi slave and wishbone bus. The issue is that the testbench file shows all the signals correctly (the signals and ports that are used in testbench) but when I am trying to check the state machine in the main code it shows nothing red line. I tried to define an output port and assign the state to it, it did not work because I don't know how to make an output port as a string because the state is like this
TYPE wb_state_t IS
(
WB_IDLE,
WB_WRITE,
WB_READ,
WB_FINISH
);
SIGNAL wb_state : wb_state_t;
I want to assign wb_state to an output port so I can check the state in the testbench.
How can I do that?
As you read in the comments, I only needed to make a simple package and put the state machine cases in it and call it in both the top level and the testbench files.
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wb_state_machine is
TYPE wb_state_t IS
(
WB_IDLE,
WB_WRITE,
WB_READ,
WB_FINISH
);
end package;
lot of simulator are able to display internal signal. for instance on vivado or Questa you can click on the design name when you are on the waves page. Then you take your signal and slide it on waves and rerun simulation
I completed Anton Potočniks' introductory guide to the red pitaya board and I am now able to send commands from the linux machine running on the SoC to its FPGA logic.
I would like to further modify the project so that I can control the phase of the signal that is being transmitted via the red pitayas' DAC. Some pins (from 7 down to 1) of the first GPIO port were still unused so I started setting them from within the OS and used the red pitaya's LEDs to confirm that they were being set without interfering with the functionality of Anton Potočnik's "high bandwidth averager".
I then set the DDS_compilers' to Phase Offset Programmability to "streaming" mode so that it can be configured on the fly using the bits that are currently controling the red pitaya's LEDs. I used some slices to connect my signals to the AXI4-Stream Constant IP core, which in turn drives the DDS compiler.
Unfortunately the DAC is just giving me a constant output of 500 mV.
I created a new project with a testbench for the DDS compiler, because synthesis takes a long time and doesn't give me much insight into what is happening.
Unfortunately all the output signals of the DDS compiler are undefined.
My question:
What am I doing wrong and how can I proceed to control DACs' phase?
EDIT1; here is my test bench
The IP core is configured as follows, so many of the control signals that I provided should not be required:
EDIT2; I changed declarations of the form m_axis_data_tready => '0' to m_axis_phase_tready => m_axis_phase_tready_signal. I also took a look at the wrapper file called dds_compiler_0.vhd and saw that it treats both m_axis_phase_tready and m_axis_data_tready as inputs.
My simulation results remained unchanged...
My new test bench can be found here.
EDIT3: Vivado was just giving me the old simulation results - creating a new testbench, deleting the file under <project_name>.sim/sim_1/behav/xsim/simulate.log and restarting vivado solved this problem.
I noticed that the wrapper file (dds_compiler_0.vhd) only has five ports:
aclk (in)
s_axis_phase_tvalid (in)
s_axis_phase_tdata (in)
m_axis_data_tvalid (out)
and m_axis_data_tdata (out)
So I removed all the unnecessary control signals and got a new simulation result, but I am still not recieving any useful output from the dds_compiler:
The corresponding testbench can be found here.
I also don't get any valid output when I include the control signals.
The corresponding testbench can be found here.
Looks like m_axis_data_tready is not connected. No data will come out unless that's asserted.
Background : ModelSim v10.4d installed with quartus v16.0
I was a Cadence Incisive user, now have to pass to mentor ModelSim, but with ModelSim I can't find a way to get all signals' data before adding them to the waveform window.
For example,
In an .do(tcl) ModelSim simmulation script, a typical flow could be:
1,vcom : compile all sources files and testbench
2,vsim : load testbench for simulation
3,view structure/signals/wave : open some windows
4,add wave : add signals to waveform window
5,run xx us : run simulation for a certain time
with this flow, I have to re-do step 5 each time adding a signal to waveform window, or it will show me "NO DATA" for that newly added signal.
So I wonder if it's possible that we skip step 4, do step 5 just once to obtain all signals' simulation data, then we choose signals to send to waveform window, and we have every signal's data without re-doing the "run".
The command you need is log. The reference manual says:
This command creates a wave log format (WLF) file containing simulation data for all HDL objects whose names match the provided specifications.
Try this flow, you can go to step 6 before the end of step 5 :
1- vcom *.vhd : compile all sources files and testbench
2- vsim work.my_tb : load testbench for simulation
3- view structure/signals/wave : open some windows
4- log * -r : tell modelsim to record everything
5- run xx us : run simulation for a certain time
6- add signals to waveform window
Using the log * -r will slow the simulation down and fill your disk up. So, you perhaps would wish to target a specific part of your design rather than using * or perhaps would wish to restrict the depth using the -depth option. Full details can be found in the Modelsim reference manual, available via the Help menu.
If you want to add every signal in the design, just do something like:
add wave -recursive -depth 10 *
This will add every signal up to 10 levels of hierarchy deep. Note that the signal logging only applies to simulation run after the add command.
In a large design, logging every signal will cause the simulation to slow down. By picking and choosing which signals you are actually interested in before running the simulation, you will get the shortest simulation run time.
You can quickly navigate the design using the 'sim' panel, then right-click an object in the 'Objects' panel to add to wave. Here you can also Add to > Wave > Signals in region, or in the 'sim' panel you can Add to > Wave > Signals in region and below.
Im attempting to use the Xilinx uartlite 2.0 IP with an AXI4-lite interface to transmit a byte without a microblaze processor. Unfortunately, all the ready signals remain low after I set the data and valid signals and the tx signal never transmits.
I've included my simulation results. any ideas?
For posterity, Had to invert the reset and ensure all the inputs were initialized. Thank you for the helpful comments. I've attached a working simulation
I am trying to re-use netlists in other designs without the success.
I have a component which is translated to the netlist:
entity c is
port (... sel : in std_logic_vector(31 downto 0); ... );
In the design I am using just sel(4 downto 0).
The synthesis tools notices this behaviour and gives a warning:
'WARNING:Xst:647 - Input sel<31:5> is never used ..
I am generating netlist with properties:
keep hierarchy = true
add I/O buffers = off
Whenever I want to instantiate this netlist as an black-box module in other circuit I got an error:
ERROR:NgdBuild:76 - cannot be merged into block because one or more pins on the block, including pin "sel<31>", were not found in the file.
How can I preserve the size of sel?
I should mention that the sel needs to be 32bits width since it's connected to the bus.
You could try driving the unused input ports to zero.
Can you use the component directly instead of as a pre-synthesised black-box?
You may get things to work by putting a KEEP attribute (see your synth tools manual) on the port. I've only ever tried this on signals, but it may work.
This sort of task is often described as "pushing on the rope" of the synthesiser, as it's such a pain to get it to not be as celever as it wants to be (and then in the next release of tools you need a different attribute :)