I'm working with a makefile where g++ defaults to using /usr/bin/g++. How do I set it to a an executable in a different path?
Same as you would in a shell script: Prepend the path to the PATH environment variable:
PATH := /other/path:$(PATH)
printpath:
env | grep PATH
Or in the calling environment:
PATH=/other/path:$PATH make ...
# or
export PATH...
make ...
Alternatively you overload the variable for g++ in the recipe (CXX) with the full path:
CXX := /other/path/g++
Related
I am trying to create shared library i.e. .so from C++ code using Git Bash shell in Windows 10.
I use Makefile for compiling C++ code in Windows 10. Running make through Git bash shell.
Code compiles without any issue and creates object files without fail.
But it fails while creating .so file throwing following error. Following is part of Makefile in which target VLIB_SHARED_LIBRARY is causing this error.
VLIB_SO_DIR = .
VLIB_SHARED_LIBRARY = $(VLIB_SO_DIR)/libvxxx.so
CXX = g++
CXXFLAGS = -Wall -std=c++11 -O2 -D_7ZIP_ST -fPIC
LDFLAGS = -shared
OBJECT_FILES = a.o b.o c.o d.o .. z.o
all: init $(VLIB_SHARED_LIBRARY )
release: init $(VLIB_SHARED_LIBRARY )
$(VLIB_SHARED_LIBRARY): $(OBJECT_FILES) \n
$(CXX) $(LDFLAGS) -o $(VLIB_SHARED_LIBRARY) $(OBJECT_DIR)/*.o
process_begin: CreateProcess(C:\Program, C:/Program Files/Git/usr/bin/sh.exe -c "g++ -shared -o C:/XXXX_YYYY/bbbb/bin_linux/libyyyy.so C:/XXXX_YYYY/bbbb/bin_linux/obj/*.o", ...) failed.
make (e=193): Error 193
Same Makefile works fine in actual Linux Ubuntu OS but fails in Windows 10.
How to fix this error ?
The reason I suggested whitespace issues in my comment above is that the error message CLEARLY shows that it's a whitespace problem:
CreateProcess(C:\Program, C:/Program Files/Git/usr/bin/sh.exe ...
There is a space in this path to sh.exe, and the first argument printed here C:\Program quite clearly shows that the path has been truncated at the space.
I thought maybe your makefile was setting SHELL to some value but it doesn't appear to be. All I can suggest is either (a) remove C:\Program Files\Git\usr\bin from your %Path%, or (b) re-install Git into a path that doesn't contain whitespace so that you don't hit this problem.
I'm trying to use a library libfoo.so that will be installed in $(LIBDIR)/foo/ where $(LIBDIR) is an environment variable that can be different based on the build setup.
In order for other components to correctly link with this library, they need to have the correct LDFLAGS set, namely they need to have -L$(LIBDIR)/foo -lfoo set. In order to make this a bit more generic, I would like to add a libfoo.pc file to libfoo with these flags set. My file currently has the following contents:
Name: libfoo
Description: Example library
Version: 1.0.0
Libs: -L$(LIBDIR)/foo -lfoo
My other component which uses libfoo has the following simplified makefile:
all:
$(CC) bar.c -o out $(shell pkg-config --libs libfoo)
The library is correctly found by pkg-config, but running make gives the following error:
$ make
cc bar.c -o out -L$(LIBDIR)/foo -lfoo
/bin/sh: LIBDIR: command not found
In other words, $(LIBDIR) is not expanded into the value that is set as an environment variable. Is it possible to use environment variables or makefile variables in .pc files?
It looks like using environment variables inside pkg-config.pc files is not possible.
As a workaround I will instead add a prefix variable to the .pc file which is filled in or overwritten by a script before my bar component is compiled.
Background: I am having a customized toolchain which shall be used by a Makefile. The toolchain is checkout out (by svn:externals) into the working copy of the project. The Makefile must adapt the PATH Variable. Otherwise the toolchain-binaries cannot be found. Adapting the ´PATH´ in ´.bashrc´ or ´.profile´ is no option because there are several projects using different versions of the toolchain.
See this little minimal Makefile demonstrating the call to the cross compiler ´cc´ which is located next to several other tools in ´/home/edeviser/bin´:
export PATH:=/home/edeviser/bin:$(PATH)$
$(info Compiler used: $(shell which cc))
all:
#echo "Compiler used: $(shell which cc)"
#echo -n "Compiler used: "
#which cc
The output after calling make:
Compiler used: /usr/bin/cc
Compiler used: /usr/bin/cc
Compiler used: /home/edeviser/bin/cc
My expectation is:
Compiler used: /home/edeviser/bin/cc
Compiler used: /home/edeviser/bin/cc
Compiler used: /home/edeviser/bin/cc
How to modify PATH in GNU Make and perform commands with $(shell ...) successfully?
You have to write a shell invocation like this:
$(info Compiler used: $(shell PATH='$(PATH)' which cc))
to set the PATH in the shell function.
Where in Debian can I find make.conf.
I do want to type following directives each time I compile.
Is there anyway to automatically set them or add them or use them during compilation.
–-host=i686-w64-mingw32
–-build=i686-w64-mingw32
--target=i686-w64-mingw32
--CROSS_COMPILE=i686-w64-mingw32
--cross-prefix=i686-w64-mingw32
--prefix=i686-w64-mingw32
-march=core2
-mtune=native
-j2
What is the difference between the following :
CARCH and ARCH
HOST and CHOST
CFLAGS and HOSTCLAG
CC and CHOSTCC
Which one is used when ?
In which files make and gcc environment variable,
global environment variable and path
bash environment variable and path are saved and where are they located.
How to set __MAKE_CONF= in debian .
How to change GCC and MAKE defaults, and set new defaults.
What is the difference between CONCURRENCY_LEVEL and MAKEFLAGS.
I'm using GNU make, and including a 3rd party library in a project that has a build system that goes berserk if CFLAGS is defined in the environment when it is called. I like to have CFLAGS defined in my environment for other reasons. The library's build is being invoked from another makefile, so that I say e.g.:
3rdparty:
$(MAKE) -f Makefile.3rdparty
But I would like to be sure that CFLAGS is unset when I invoke make on the 3rd party Makefile. The nearest thing I can find is to say:
CFLAGS:=
But this still leaves CFLAGS set in the environment, it's just an empty string. Apart
from doing something hideous like saying:
3rdparty:
bash -c "unset CFLAGS; $(MAKE) -f Makefile.3rdparty"
Is there an easy way to "unset" the CFLAGS variable from within my primary makefile, so that it isn't present at all in the environment when the third party library is invoked?
Doesn't the following work for you?
unexport CFLAGS
3rdparty:
$(MAKE) -f Makefile.3rdparty
As of version 3.82 make has an "undefine" directive:
undefine CFLAGS
This can be problematic if you need the variable to be defined for other commands in the recipe and only don't want it defined in the submake. Another solution is to use env - to invoke the submake and explicitly set any environment variables you need set in the submake, eg:
env - PATH="$$PATH" LD_LIBRARY_PATH="$$LD_LIBRARY_PATH" $(MAKE) -f Makefile.3rdparty
To unset an Environment variable in linux.
Use:
export -n MY_ENV_VARIABLE