I've made a design in platform design in quartus ver 18.0 and I want to instantiate it in a template design I made for the MAX10DE10 lite development kit
I try to compile it and it gives me this error:
Error (10170): Verilog HDL syntax error at DE10_LITE_Golden_Top.sv(2)
near text: "("; expecting ";". Check for and fix any syntax errors
that appear immediately before or at the specified keyword. The Intel
FPGA Knowledge Database contains many articles with specific details
on how to resolve this error. Visit the Knowledge Database at
https://www.altera.com/support/support-resources/knowledge-base/search.html
and search for this specific error message number.
I made a soft processor design in platform design called core and the core_inst.v verilog file is as follows:
core u0 (
.altpll_1_areset_conduit_export (<connected- to- altpll_1_areset_conduit_export>), //` altpll_1_areset_conduit.export
.altpll_1_locked_conduit_export (<connected-to-altpll_1_locked_conduit_export>), // altpll_1_locked_conduit.export
.clk_clk (<connected-to-clk_clk>), // clk.clk
.clk_0_clk (<connected-to-clk_0_clk>), // clk_0.clk
.pio_0_external_connection_export (<connected-to-pio_0_external_connection_export>), // pio_0_external_connection.export
.pio_1_external_connection_export (<connected-to-pio_1_external_connection_export>), // pio_1_external_connection.export
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
.reset_0_reset_n (<connected-to-reset_0_reset_n>), // reset_0.reset_n
.altpll_0_c1_clk (<connected-to-altpll_0_c1_clk>) // altpll_0_c1.clk
);
The code for the template is:
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define ENABLE_ADC_CLOCK
`define ENABLE_CLOCK1
`define ENABLE_CLOCK2
`define ENABLE_SDRAM
`define ENABLE_HEX0
`define ENABLE_HEX1
`define ENABLE_HEX2
`define ENABLE_HEX3
`define ENABLE_HEX4
`define ENABLE_HEX5
`define ENABLE_KEY
`define ENABLE_LED
`define ENABLE_SW
`define ENABLE_VGA
`define ENABLE_ACCELEROMETER
`define ENABLE_ARDUINO
`define ENABLE_GPIO
module DE10_LITE_Golden_Top(
//////////// ADC CLOCK: 3.3-V LVTTL //////////
`ifdef ENABLE_ADC_CLOCK
input ADC_CLK_10,
`endif
//////////// CLOCK 1: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK1
input MAX10_CLK1_50,
`endif
//////////// CLOCK 2: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK2
input MAX10_CLK2_50,
`endif
//////////// SDRAM: 3.3-V LVTTL //////////
`ifdef ENABLE_SDRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
//////////// SEG7: 3.3-V LVTTL //////////
`ifdef ENABLE_HEX0
output [7:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [7:0] HEX1,
`endif
`ifdef ENABLE_HEX2
output [7:0] HEX2,
`endif
`ifdef ENABLE_HEX3
output [7:0] HEX3,
`endif
`ifdef ENABLE_HEX4
output [7:0] HEX4,
`endif
`ifdef ENABLE_HEX5
output [7:0] HEX5,
`endif
//////////// KEY: 3.3 V SCHMITT TRIGGER //////////
`ifdef ENABLE_KEY
input [1:0] KEY,
`endif
//////////// LED: 3.3-V LVTTL //////////
`ifdef ENABLE_LED
output [9:0] LEDR,
`endif
//////////// SW: 3.3-V LVTTL //////////
`ifdef ENABLE_SW
input [9:0] SW,
`endif
//////////// VGA: 3.3-V LVTTL //////////
`ifdef ENABLE_VGA
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS,
`endif
//////////// Accelerometer: 3.3-V LVTTL //////////
`ifdef ENABLE_ACCELEROMETER
output GSENSOR_CS_N,
input [2:1] GSENSOR_INT,
output GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
//////////// Arduino: 3.3-V LVTTL //////////
`ifdef ENABLE_ARDUINO
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
//////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL //////////
`ifdef ENABLE_GPIO
inout [35:0] GPIO
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
And the entire code with the instantiation is:
core u3 (
.altpll_1_areset_conduit_export (<connected-to-altpll_1_areset_conduit_export>), // altpll_1_areset_conduit.export
.altpll_1_locked_conduit_export (<connected-to-altpll_1_locked_conduit_export>), // altpll_1_locked_conduit.export
.clk_clk (<connected-to-clk_clk>), // clk.clk
.clk_0_clk (<connected-to-clk_0_clk>), // clk_0.clk
.pio_0_external_connection_export (<connected-to-pio_0_external_connection_export>), // pio_0_external_connection.export
.pio_1_external_connection_export (<connected-to-pio_1_external_connection_export>), // pio_1_external_connection.export
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
.reset_0_reset_n (<connected-to-reset_0_reset_n>), // reset_0.reset_n
.altpll_0_c1_clk (<connected-to-altpll_0_c1_clk>) // altpll_0_c1.clk
);
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define ENABLE_ADC_CLOCK
`define ENABLE_CLOCK1
`define ENABLE_CLOCK2
`define ENABLE_SDRAM
`define ENABLE_HEX0
`define ENABLE_HEX1
`define ENABLE_HEX2
`define ENABLE_HEX3
`define ENABLE_HEX4
`define ENABLE_HEX5
`define ENABLE_KEY
`define ENABLE_LED
`define ENABLE_SW
`define ENABLE_VGA
`define ENABLE_ACCELEROMETER
`define ENABLE_ARDUINO
`define ENABLE_GPIO
module DE10_LITE_Golden_Top(
//////////// ADC CLOCK: 3.3-V LVTTL //////////
`ifdef ENABLE_ADC_CLOCK
input ADC_CLK_10,
`endif
//////////// CLOCK 1: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK1
input MAX10_CLK1_50,
`endif
//////////// CLOCK 2: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK2
input MAX10_CLK2_50,
`endif
//////////// SDRAM: 3.3-V LVTTL //////////
`ifdef ENABLE_SDRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
//////////// SEG7: 3.3-V LVTTL //////////
`ifdef ENABLE_HEX0
output [7:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [7:0] HEX1,
`endif
`ifdef ENABLE_HEX2
output [7:0] HEX2,
`endif
`ifdef ENABLE_HEX3
output [7:0] HEX3,
`endif
`ifdef ENABLE_HEX4
output [7:0] HEX4,
`endif
`ifdef ENABLE_HEX5
output [7:0] HEX5,
`endif
//////////// KEY: 3.3 V SCHMITT TRIGGER //////////
`ifdef ENABLE_KEY
input [1:0] KEY,
`endif
//////////// LED: 3.3-V LVTTL //////////
`ifdef ENABLE_LED
output [9:0] LEDR,
`endif
//////////// SW: 3.3-V LVTTL //////////
`ifdef ENABLE_SW
input [9:0] SW,
`endif
//////////// VGA: 3.3-V LVTTL //////////
`ifdef ENABLE_VGA
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS,
`endif
//////////// Accelerometer: 3.3-V LVTTL //////////
`ifdef ENABLE_ACCELEROMETER
output GSENSOR_CS_N,
input [2:1] GSENSOR_INT,
output GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
//////////// Arduino: 3.3-V LVTTL //////////
`ifdef ENABLE_ARDUINO
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
//////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL //////////
`ifdef ENABLE_GPIO
inout [35:0] GPIO
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
To make the instantiation of the core the block should be putted just above the endmodule like this
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define ENABLE_ADC_CLOCK
`define ENABLE_CLOCK1
`define ENABLE_CLOCK2
`define ENABLE_SDRAM
`define ENABLE_HEX0
`define ENABLE_HEX1
`define ENABLE_HEX2
`define ENABLE_HEX3
`define ENABLE_HEX4
`define ENABLE_HEX5
`define ENABLE_KEY
`define ENABLE_LED
`define ENABLE_SW
`define ENABLE_VGA
`define ENABLE_ACCELEROMETER
`define ENABLE_ARDUINO
`define ENABLE_GPIO
module DE10_LITE_Golden_Top(
//////////// ADC CLOCK: 3.3-V LVTTL //////////
`ifdef ENABLE_ADC_CLOCK
input ADC_CLK_10,
`endif
//////////// CLOCK 1: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK1
input MAX10_CLK1_50,
`endif
//////////// CLOCK 2: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK2
input MAX10_CLK2_50,
`endif
//////////// SDRAM: 3.3-V LVTTL //////////
`ifdef ENABLE_SDRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
//////////// SEG7: 3.3-V LVTTL //////////
`ifdef ENABLE_HEX0
output [7:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [7:0] HEX1,
`endif
`ifdef ENABLE_HEX2
output [7:0] HEX2,
`endif
`ifdef ENABLE_HEX3
output [7:0] HEX3,
`endif
`ifdef ENABLE_HEX4
output [7:0] HEX4,
`endif
`ifdef ENABLE_HEX5
output [7:0] HEX5,
`endif
//////////// KEY: 3.3 V SCHMITT TRIGGER //////////
`ifdef ENABLE_KEY
input [1:0] KEY,
`endif
//////////// LED: 3.3-V LVTTL //////////
`ifdef ENABLE_LED
output [9:0] LEDR,
`endif
//////////// SW: 3.3-V LVTTL //////////
`ifdef ENABLE_SW
input [9:0] SW,
`endif
//////////// VGA: 3.3-V LVTTL //////////
`ifdef ENABLE_VGA
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS,
`endif
//////////// Accelerometer: 3.3-V LVTTL //////////
`ifdef ENABLE_ACCELEROMETER
output GSENSOR_CS_N,
input [2:1] GSENSOR_INT,
output GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
//////////// Arduino: 3.3-V LVTTL //////////
`ifdef ENABLE_ARDUINO
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
//////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL //////////
`ifdef ENABLE_GPIO
inout [35:0] GPIO
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
core u3 (
.altpll_1_areset_conduit_export (ARDUINO_IO[2]), // altpll_1_areset_conduit.export
.altpll_1_locked_conduit_export (ARDUINO_IO[3]), // altpll_1_locked_conduit.export
.clk_clk (MAX10_CLK1_50), // clk.clk
.clk_0_clk (ADC_CLK_10), // clk_0.clk
.pio_0_external_connection_export (LEDR), // pio_0_external_connection.export
.pio_1_external_connection_export (sw), // pio_1_external_connection.export
.reset_reset_n (ARDUINO_RESET_N), // reset.reset_n
.reset_0_reset_n (ARDUINO_RESET_n), // reset_0.reset_n
.altpll_0_c1_clk () // altpll_0_c1.clk
);
endmodule
This design compiles and disappears the error 10170
Related
Why do I get syntax errors in my Verilog code?
The code:
module RegFile (
input clk,
input [4:0] rs1,
input [4:0] rs2,
input [4:0] wr,
input reg[31:0] wd,
input RegWrite,
output reg[31:0] rd1,
output reg[31:0] rd2);
reg [31:0] file[31:0];
integer i;
initial begin
i=0;
while(i<32)
begin
file[i]=32'b0;
i=i+1;
end
assign rd1=file[rs1];
assign rd2=file[rs2];
always #(posedge clk) begin
if(RegWrite)
file[wr]=wd;
end
always#(file[0])
file[0]=32'b0;
endmodule
Here are the errors:
regfile.v:25: syntax error
regfile.v:27: Syntax in assignment statement l-value.
The "l-value" syntax error happens because you make continuous assignments (using the assign keyword) to signals you declared as reg. You should not use the reg keyword in this case. Change:
output reg[31:0] rd1,
output reg[31:0] rd2);
to:
output [31:0] rd1,
output [31:0] rd2);
I also get a compile error on the following line:
input reg[31:0] wd,
You should not use the reg keyword for an input port. Change it to:
input [31:0] wd,
Finally, you are missing the matching end keyword for the while begin:
initial begin
i=0;
while(i<32)
begin
file[i]=32'b0;
i=i+1;
end // <----- add this
end
You can sign up for a free account on edaplayground to gain access to simulators which will give you more specific error messages.
I am trying to instantiate a VHDL component in a Verilog design as a part of testing a divide function in another complex design. Getting syntax error:
Error (10170): Verilog HDL syntax error at deldel.v(29) near text:
"["; expecting ")".......
My VHDL file:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity divide_test is
port(
odabir : in std_logic_vector(9 downto 0);
rezultat : out std_logic_vector(9 downto 0)
);
end divide_test;
architecture behavioral of divide_test is
constant deljenik0 : unsigned(23 downto 0) := x"000999"; --2457
constant deljenik1 : unsigned(23 downto 0) := x"000FA7"; --4007
constant deljenik2 : unsigned(23 downto 0) := x"000288"; --648
constant delilac : unsigned(23 downto 0) := x"000015"; --21
signal rez_temp : unsigned(23 downto 0);
signal od_temp : integer range 0 to 3;
begin
od_temp <= to_integer(unsigned(odabir));
rezultat <= std_logic_vector(rez_temp(9 downto 0));
deljenje: process(od_temp)
begin
case od_temp is
when 0 => rez_temp <= x"000000";
when 1 => rez_temp <= deljenik0/delilac; --150
when 2 => rez_temp <= deljenik1/delilac; --200
when 3 => rez_temp <= deljenik2/delilac; --32
end case;
end process;
end behavioral;
My Verilog file:
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module deldel(
//////////// LED //////////
output [9:0] LEDR,
//////////// SW //////////
input [9:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
divide_test u0(
.odabir[1] (SW[0]),
.odabir[0] (SW[1]),
.rezultat[0] (LEDR[0]),
.rezultat[1] (LEDR[1]),
.rezultat[2] (LEDR[2]),
.rezultat[3] (LEDR[3]),
.rezultat[4] (LEDR[4]),
.rezultat[5] (LEDR[5]),
.rezultat[6] (LEDR[6]),
.rezultat[7] (LEDR[7]),
);
endmodule
Verilog file is generic, created from "DE1SoC_SystemBuilder". I am trying to connect SW0 and SW1 from DE1Soc board to select one from three operation and show the result with eight LEDs on DE1Soc board!
What am I missing?
The error message indicates that you should not use square brackets for the instance port names (odabir and rezultat) in the Verilog module. You should not split out the bits of the signals in the instance port names. Refer to the IEEE Std 1800-2017, section 23.3.2.2 Connecting module instance ports by name, which states:
The port_name shall be the name specified in the module declaration.
The port name cannot be a bit-select, a part-select, or a
concatenation of ports.
You could use square brackets for the connecting signals (SW and LEDR). However, since the signals are all 10 bits wide, it is simpler to just use the signal name:
divide_test u0 (
.odabir (SW),
.rezultat (LEDR)
);
Note that you can use a range specifier for the connecting signals (SW, for example):
divide_test u0 (
.odabir (SW[9:0]),
.rezultat (LEDR[9:0])
);
You can have any valid expression for the connecting signals (inside the parentheses).
I find an answer! Originaly my ports:
odabir : in std_logic_vector(9 downto 0)
rezultat : out std_logic_vector(9 downto 0)
was two and eight bits wide, respectively:
odabir : in std_logic_vector(1 downto 0)
rezultat : out std_logic_vector(7 downto 0)
I change that in process to figure it out error code; trying to match lenght with De1Soc board ports SW and LEDR.
The solution code will be:
divide_test u0(
.odabir ({SW[1], SW[0]}),
.rezultat ({LEDR[7], LEDR[6], LEDR[5], LEDR[4], LEDR[3], LEDR[2], LEDR[1], LEDR[0]})
);
Still I didnt find out why I cant split bits of ports od divide_test module that is being instantiate!?
module alucontrol(iw,cntrl,Ra,Rb,Wa);
input [14:0]iw;
output reg [3:0]cntrl;
output reg [3:0]Ra;
output reg [3:0]Rb;
output reg [3:0]Wa;
always#(*)
begin
cntrl=iw[14:12];
Ra=iw[11:8];
Rb=iw[7:4];
Wa=iw[3:0];
end
endmodule
////////////////////////////////////////////
module alumemory(Ra,Rb,Wa,A,B);
input wire [3:0]Ra,Rb,Wa;
output reg [3:0]A,B;
reg [3:0] mem [0:15];
reg array[3:0][0:15];
always#(*)
begin
array[3:0][0]=4'b0100;
array[3:0][1]=4'b1001;
array[3:0][2]=4'b0110;
array[3:0][3]=4'b0010;
array[3:0][4]=4'b0100;
array[3:0][5]=4'b1101;
array[3:0][6]=4'b0100;
array[3:0][7]=4'b0001;
array[3:0][8]=4'b0000;
array[3:0][9]=4'b1111;
array[3:0][10]=4'b1000;
array[3:0][11]=4'b1001;
array[3:0][12]=4'b1000;
array[3:0][13]=4'b1011;
array[3:0][14]=4'b1100;
array[3:0][15]=4'b1010;
end
integer my_int1;
always#(1)
begin
my_int1=Ra;
A[3:0]=array[3:0][my_int1];
end
integer my_int2;
always#(1)
begin
my_int2=Rb;
B[3:0]=array[3:0][my_int2];
end
integer my_int3;
always#(1)
begin
my_int3=Wa;
array[3:0][my_int3]=C[3:0];
end
endmodule
////////////////////////////////////
module Decoder(cntrl[3:0],adden, suben, mulen, diven, anden, oren, xoren, noten);
input [3:0]cntrl;
output adden, suben, mulen, diven, anden, oren, xoren, noten;
assign adden=(~a&~b&~c),
suben=(~a&~b&c),
mulen=(~a&b&~c),
diven=(~a&b&c),
anden=(a&~b&~c),
oren=(a&~b&c),
xoren=(a&b&~c),
noten=(a&b&c);
endmodule
//////////////////////////////////////////////////
module alu_arith(input[3:0]A,
input adden, input suben,input mulen,input diven,input anden,input oren,input xoren,input noten,
input[3:0]B,
output reg [7:0]C
);
reg cntrlinp[7:0];
//wire[3:0]A;
//wire[3:0]B;
assign cntrlinp[0]=adden,
cntrlinp[1]=suben,
cntrlinp[2]=mulen,cntrlinp[3]=diven,cntrlinp[4]=anden,cntrlinp[5]=oren,cntrlinp[6]=xoren,cntrlinp[7]=noten;
always#(*)
begin
case(ctrlinp[7:0])
00000001:C=A+B;
00000010:C=A-B;
00000100:C=A*B;
00001000:C=A/B;
00010000:C=A&B;
00100000:C=A|B;
01000000:C=A^B;
10000000:C=~A;
default: C=8'b00000001;
endcase
end
endmodule
///////////////////////////////////////////////////////
module testbench;
reg[14:0]iw;
wire[7:0]C;
alucontrol a1(iw, cntrl,Ra,Rb,Wa);
alumemory a2(Ra,Rb,Wa,A,B);
alu_arith a3(A,B,C);
Decoder a4(cntrl,adden, suben, mulen, diven, anden, oren, xoren, noten);
initial begin
$display("time\t A B cntrl C");
$monitor("%g\t %b %b %b %b",
$time, A, B, cntrl, C);
#0 C=8'b00000000;
iw=15'b101000101011010;
#5 iw=15'b001100110011001;
#10 iw=15'b010101110101110;
end
endmodule
So i'm trying to make a very basic design of a processor(a simple ALU with register file and control unit) where the control unit takes the opcode, divides it into iw(instruction word), Ra(Read A),Rb(Read B) and Wa(Write A) and sends the last three of those to the register file to write/read registers.
The parameters that are output for control unit are input for register file, and my code is repeatedly giving the following error in two lines after alumemory module begins:
syntax error
error: Invalid variable list in port declaration.
I don't understand what's exactly causing a syntax error. Please help.
I've created a 2d array for register file and I'm accessing it using the following block:
integer my_int2;
always#(1)
begin
my_int2=Rb;
B[3:0]=array[3:0][my_int2];
end
I think I've declared ports and wire and reg in an appropriate way.
module alucontrol(iw,cntrl,Ra,Rb,Wa);
input [14:0]iw;
output [3:0]cntrl;
output[3:0]Ra;
output[3:0]Rb;
output[3:0]Wa;
reg [3:0]Ra;
reg [3:0]Rb;
reg [3:0]Wa;
reg [3:0]cntrl;
always#(*)
begin
cntrl=iw[14:12];
Ra=iw[11:8];
Rb=iw[7:4];
Wa=iw[3:0];
end
endmodule
////////////////////////////////////////////
module alumemory(Ra,Rb,Wa,A,B);
input [3:0]Ra,input [3:0]Rb;input [3:0]Wa;
output[3:0]A;output [3:0]B;
wire [3:0]Ra; wire [3:0]Rb; wire [3:0]Wa;
reg[3:0]A;
reg[3:0]B;
reg [3:0] mem [0:15];
reg array[3:0][0:15];
always#(*)
begin
array[3:0][0]=4'b0100;
array[3:0][1]=4'b1001;
array[3:0][2]=4'b0110;
array[3:0][3]=4'b0010;
array[3:0][4]=4'b0100;
array[3:0][5]=4'b1101;
array[3:0][6]=4'b0100;
array[3:0][7]=4'b0001;
array[3:0][8]=4'b0000;
array[3:0][9]=4'b1111;
array[3:0][10]=4'b1000;
array[3:0][11]=4'b1001;
array[3:0][12]=4'b1000;
array[3:0][13]=4'b1011;
array[3:0][14]=4'b1100;
array[3:0][15]=4'b1010;
end
integer my_int1;
always#(1)
begin
my_int1=Ra;
A[3:0]=array[3:0][my_int1];
end
integer my_int2;
always#(1)
begin
my_int2=Rb;
B[3:0]=array[3:0][my_int2];
end
integer my_int3;
always#(1)
begin
my_int3=Wa;
array[3:0][my_int3]=C[3:0];
end
endmodule
Declare your ports this in this much simpler way:
module alumemory(
input wire [3:0] Ra, Rb, Wa,
output reg [3:0] A,B
);
reg [3:0] mem [0:15];
reg array[3:0][0:15];
...
I use AXI IIC BUS IP Core on vivado.Even if I write the corresponding data to the register, there is no change on the sda data line.
Here is the registers of the ip core.
Register of AXI IIC
And the Programming Sequence are as below.
The sequence
It seems that I only need to complete the first and the second steps and I can see the wavefrom changes on SDA
Here is a top.v （it's not my original,reference from Bad s_axi_bvalid, s_axi_wready, and s_axi_awready signals using Vivado IIC IP Flow）
module i2c_channel #(
parameter CHANNEL_OUTPUT_WIDTH = 16
)(
input clk,
input reset,
//the address of the slave;
input [6:0] slave_address,
//The width of the message expected from the slave at the specified address;
input [127:0] slave_message_width,
inout sda,
inout scl,
output [CHANNEL_OUTPUT_WIDTH - 1:0] channel_output
);
wire iic2intc_irpt ;
//AXI Global System Signals
wire s_axi_aclk;
assign s_axi_aclk = clk;
reg s_axi_aresetn ;
//AXI Write Address Channel Signals
reg [31:0] s_axi_awaddr ;
reg s_axi_awvalid ;
wire s_axi_awready;
//AXI Write Data Channel Signals
reg [31:0] s_axi_wdata ;
reg [3:0] s_axi_wstrb ;
reg s_axi_wvalid ;
wire s_axi_wready;
//AXI Write Response Channel Signals
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
reg s_axi_bready ;
//AXI Read Address Channel Signals
reg [31:0] s_axi_araddr ;
reg s_axi_arvalid ;
wire s_axi_arready;
//AXI Read Data Channel Signals
wire [31:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rvalid;
reg s_axi_rready ;
//IIC signals
reg sda_i ;
wire sda_o;
wire sda_t;
reg scl_i ;
wire scl_o;
wire scl_t;
reg gpo ;
reg state_done;
//i2C state
`define SET_TX_FIFO 4'b0000
`define SET_RX_FIFO_PIRQ 4'b0001
`define SET_CR_MSMS_TX 4'b0010
`define SET_CR_TXAK 4'b0011
reg[3:0]state;
initial begin
state<=4'b0000;
end
//tri-state open-collector buffers to convert the iic signals to bi-directional inouts.
assign sda = sda_t ? sda_o : sda_i;
assign sda = scl_t ? scl_o : scl_i;
axi_iic_1 iic (
.iic2intc_irpt(),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr[8:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rdata(s_axi_rdata),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rresp(s_axi_rresp),
.sda_i(sda_i),
.sda_o(sda_o),
.sda_t(sda_t),
.scl_i(scl_i),
.scl_o(scl_o),
.scl_t(scl_t)
);
always #(clk) begin
s_axi_aresetn <= ~reset;
end
//Sets an axi data write operation.
task set_a_axi_w ;
input [31:0] awaddr;
input [31:0] wdata;
begin
s_axi_awaddr = awaddr;
s_axi_wdata = wdata;
s_axi_awvalid = 1'b1;
s_axi_bready = 1'b1;
s_axi_wvalid = 1'b1;
end
endtask
//set the state of the operation.
task set_state ;
input[3:0] new_state;
if(s_axi_awready) begin
state = new_state;
end
endtask
//when the module is initialized, write the i2c address of the target slave to the TX_FIFO register.
//Write the IIC peripheral device addresses for the first slave device to the TX_FIFO.
always #(posedge clk) begin
case (state)
`SET_TX_FIFO : begin
set_a_axi_w(32'h108, slave_address);
set_state(`SET_RX_FIFO_PIRQ);
end
`SET_RX_FIFO_PIRQ : begin
set_a_axi_w(32'h120, slave_message_width - 2);
set_state(`SET_CR_MSMS_TX);
end
`SET_CR_MSMS_TX : begin
set_a_axi_w(32'h100, 8'b00000101);
set_state(`SET_CR_TXAK);
end
endcase
if(s_axi_awready) begin
//s_axi_awaddr <= '0;
s_axi_awvalid <= 1'b0;
end
if(s_axi_wready) begin
//s_axi_wdata <= '0;
s_axi_wvalid <= 1'b0;
end
if (s_axi_bvalid) begin
s_axi_bready <= 1'b0;
end/**
else begin
s_axi_bready <=1'b0;
end**/
end
endmodule
Here is the simulation file：
module i2c_channel_tb();
//Parameters
parameter CLK_PERIOD = 10;
reg clk = 1'b1;
reg reset = 1'b1;
reg [6:0] slave_address = 6'b0;
wire sda;
wire scl;
i2c_channel i2c_channel_1 (
.clk(clk),
.reset(reset),
.slave_address(slave_address),
.slave_message_width(128'd16),
.sda(sda),
.scl(scl)
);
/*
i2c_channel_slave_model i2c_channel_slave_model_1 (
.sda(sda),
.scl(scl)
);**/
initial begin
clk <= 1'b0;
reset <= 1'b0;
slave_address <= 7'b100_1011;
end
//psuedo-clock
always #10 begin
clk <= ~clk;
end
endmodule
the waveform result is below：
Result waveform
As shown in the figure，the data is written to the register，but no changes occur on the sda_o and scl_o.
Could anybody tell me why?
Thanks！
One obvious mistake is that your SDA and SCL should be pulled up in their initial state.
Your waveform shows that sda_o, sda_i, scl_o, and scl_i are not pulled up at any given time. So perhaps you need to check that. (Either it is some hardware schematic to check, or some IO constraint to set.)
My code consists of two files. One file has all the modules and one file has the test bench. When I try to run a simulation on the test bench, I get an unresolved reference error on this line in one of my modules:
Add_half (p[3], g[3], in_a[3], in_b[3]);
This line occurs in the module that my test bench calls.
What could be the problem?
This is the code for the test bench.
`timescale 1ns/100ps
module CARRYLOOKAHEAD_TB;
reg [3:0] in_a_tb;
reg [3:0] in_b_tb;
reg in_c0_tb;
wire [3:0] s_tb;
wire c4_tb;
CarryLookAheadAdder DUT (.in_a(in_a_tb), .in_b(in_b_tb), .in_c0(in_c0_tb), .out_s(s_tb), .out_c4(c4_tb));
initial
begin
in_a_tb = 4'b0000;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50
in_a_tb = 4'b0000;
in_a_tb = 4'b0001;
in_c0_tb = 1'b1;
#50
in_a_tb = 4'b0001;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50
in_a_tb = 4'b1111;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50
in_a_tb = 4'b1111;
in_a_tb = 4'b0000;
in_c0_tb = 1'b1;
#50 $stop;
#20 $finish;
end
endmodule
This is the code for the module
module Add_half (sum, c_out, a, b);
input a, b;
output c_out, sum;
assign sum = a ^ b;
assign c_out = a & b;
endmodule
This is what gets called by the test bench
module CarryLookAheadAdder (in_a, in_b, in_c0, out_s, out_c4);
input [3:0] in_a;
input [3:0] in_b;
input in_c0;
output reg [3:0] out_s;
output reg out_c4;
reg [3:0] p;
reg [3:0] g;
reg [3:0] c;
always#(in_a, in_b, in_c0)
begin
out_s[0] = (in_a[0] ^ in_b[0]) ^ in_c0;
Add_half (p[3], g[3], in_a[3], in_b[3]);
Add_half (p[2], g[2], in_a[2], in_b[2]);
Add_half (p[1], g[1], in_a[1], in_b[1]);
Add_half (p[0], g[0], in_a[0], in_b[0]);
out_c4 = c[4];
out_s[3] = p[3] ^ c[3];
out_s[2] = p[2] ^ c[2];
out_s[1] = p[1] ^ c[1];
out_s[0] = p[0] ^ c[0];
end
endmodule
You're missing an instance name. Your simulator probably thinks that statement is a UDP instance so it gives an unresolved reference error during design elaboration. Compilation does not resolve module/UDP instances with definitions so these errors won't cause the compile to fail.
Try
Add_half add_half_inst(p[3], g[3], in_a[3], in_b[3]);
EDIT:
Add_half is not a function or a task and can't be placed in an always block. It is a module and thus is instanced, not called. Remember you're modeling a logic circuit here.
Add_half add_half_0(p[3], g[3], in_a[3], in_b[3]);
Add_half add_half_1(p[3], g[3], in_a[3], in_b[3]);
...
Notice each instance has a unique name. You're instancing the same circuit 4 times and simply wiring the inputs and outputs. The instance name is required so they can be uniquely resolved using hierarchical identifiers.
This won't work as c is [3:0]
out_c4 = c[4];
Someone might mention a loop but I think you should ignore those for now even though they are appropriate here.
In addition to Adam12 & GuanoLoco, just some general notes:
You are assign out_s[0] twice your CarryLookAheadAdder module
out_s[0] = (in_a[0] ^ in_b[0]) ^ in_c0;
...
out_s[0] = p[0] ^ c[0];
You aren't using your "g" variable output anywhere. You probably want this to be your "c", as I'm guessing this is your carry.
In addition to the steps mentioned in Adam12's answer (add instance names, move out of always block), you need to change the type on your connection wires.
reg [3:0] p;
reg [3:0] g;
should be
wire [3:0] p;
wire [3:0] g;
This is because these are connected directly to the ports on the module. You would only use reg for something that was assigned in the always block.