VHDL: need to calculate float variables in VHDL - vhdl

Question

I am new to VHDL, for my project I need to use float value. I have used variable data type in my design. To have float value I can use real data type, but real data type is not synthesizable. In the below I have given my code. In cA part I am dividing it by 2, where I need to have float number. But the vivado software is rounding off the number. Also, after cA part, I need to multiply cA with sqrt 2, which is a float number.
After the calculation I need to send these data through AXI peripheral.
Is there any solution where I can have float number in my VHDL code?
Thanks a lot.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.numeric_std.signed;
use IEEE.MATH_REAL.ALL;
entity sinewave_dwt is
Port ( clk : in STD_LOGIC;
dataout : out integer range 0 to 127);
end sinewave_dwt;
architecture Behavioral of sinewave_dwt is
signal cA_A : integer :=0;
signal cD_D : integer :=0;
signal i : integer :=0;
begin
process(clk)
variable cA : integer :=0;
variable cD : integer :=0;
type memory_type is array (0 to 7) of integer range 0 to 127;
variable sine : memory_type :=(4,6,10,12,8,6,5,6);
begin
if(rising_edge(clk)) then
cA := sine(i) + sine(i+1);
cA := cA/2;
cA_A <= cA;
report "cA: " & integer'image(cA);
cD := sine(i) - sine(i+1);
cD := cD/2;
cD_D <= cD;
report "cD: " & integer'image(cD);
i <= i + 2;
if(i > 7) then
cA := 0;
cD := 0;
i <= 0;
end if;
end if;
end process;
end Behavioral;

Answer 1

Vhdl cannot synthesize floating numbered codes because to be able to work with floating numbers, either you need to design a FPU (floating point unit) or just work with fixed point integer arithmetic. You need to determine your minimum and maximum numbers you are working. For example, if your range is 0.01 and 30, then convert minimum floating number you work to integer number by multiplying it 100. Then, your new range will be 100*(0.01-30) => 1-3000. If you want to 5/2 operation, this means 500/2 = 250.