Problem
This is my Makefile:
SRC=src/main.tex
DST_DIR=bin
ENGINE=latexmk
FLAGS=-synctex=1 --interaction=nonstopmode -file-line-error -xelatex -cd -outdir=../$(DST_DIR)
all:
$(ENGINE) $(FLAGS) -usepretex="\def\foo{1}\def\bar{0}" -jobname="all" $(SRC)
When I run target all,
$ make all
latexmk -synctex=1 --interaction=nonstopmode -file-line-error -xelatex -cd -outdir=../bin -usepretex="\def\foo{1}\def\bar{1}" -jobname="all" src/main.tex
Rc files read:
NONE
Latexmk: This is Latexmk, John Collins, 20 November 2021, version: 4.76.
Latexmk: Changing directory to 'src/'
Latexmk: applying rule 'xelatex'...
Rule 'xelatex': File changes, etc:
Changed files, or newly in use since previous run(s):
'main.tex'
------------
Run number 1 of rule 'xelatex'
------------
------------
Running 'xelatex -no-pdf -synctex=1 --interaction=nonstopmode -file-line-error -recorder --jobname="all" -output-directory="<my-project-dir>/bin" "deffoo1defbar1\input{main.tex}"'
------------
This is XeTeX, Version 3.141592653-2.6-0.999993 (TeX Live 2021/W32TeX) (preloaded format=xelatex)
restricted \write18 enabled.
entering extended mode
! I can't find file `deffoo1defbar1'.
<to be read again>
\let
<*> deffoo1defbar1\input
{main.tex}
(Press Enter to retry, or Control-Z to exit)
Please type another input file name
! Emergency stop.
<to be read again>
\let
<*> deffoo1defbar1\input
{main.tex}
You can see pretex \def\foo{1}\def\bar{1} was correctly delivered to latexmk, but changed to deffoo1defbar1 on executing xelatex command, i.e. backslashes and braces are ignored.
What could be the possible problem and solution to this issue?
What I've tried so far
Executed the whole command(below) directly, instead of using latexmk: Worked
Substitued actual values to macros on Makefile: Not worked (Same error)
Executed on another Windows device: Worked
$ latexmk -synctex=1 --interaction=nonstopmode -file-line-error -xelatex -cd -outdir=../bin -usepretex="\def\foo{1}\def\bar{1}" -jobname="all" src/main.tex
Additional Mysterious Results
I have Makefile A for project A, Makefile B for project B, and both latexmk command in Makefiles uses pretex with backslashes and braces. I also have two Windows 10 devices X and Y. When I run Makefiles on my devices...
Run Makefile A on device X: Not works (the problem in the post)
Run Makefile A on device Y: Works
Run Makefile B on device X: Works
Run Makefile B on device Y: Works
I have no idea why only Makefile A does not work on only device X.
I just solved the problem; the problem was from "optional Unix tools" when installing git. git was installed with optional Unix tools on device X, without tools on device Y.
I reinstalled git without tools on device X, and the script worked.
Related
I have seen this question and has read its many answers. I understand that this problem usually (always??) appears because of a mistake in using tabs vs spaces in Makefiles. So far that is the general case.
In my case, I have found the error in the title but not when doing make with a Makefile I suspect.
I do:
make a_configuration_file
and I get
Makefile:1: *** missing separator. Stop.
I suppose this "1" means that the error is occurring in the first line of the file, right?
This a_configuration_file is actually a generated file and the first lines are copied here :
#
# Automatically generated file; DO NOT EDIT.
# Ambarella SDK Configuration
#
CONFIG_THREADX=y
CONFIG_BOOT_CORE_SRTOS=0
So my questions for my particular case are:
The "1" refers to the comment line "#"? or the CONFIG_THREADX line?
This configuration file is not using Tabs. So what could be the problem?
EDIT:
Robert tells me that the problem could be the end-of-line. I checked with cat -A a_configuration_file and it seems there are no \r characters (I ve had problems with this before so I learned how to check for end-of-line chars)
Wander Nauta tells me the problem is in the Makefile. Which Makefile should I check? Right now there is a Makefile in the directory from where I call make and it is like this
build/Makefile
no tabs or spaces
I also did cat -A Makefile and I got
build/Makefileroot#themachine.....
If you are wondering what is that, is just that it seems that the Makefile does not have an end of the line at the end, so the cat command prints the contents and the rest (root#themachine...) is just the normal line in the command line
EDIT2:
I think I am close to finding the error.
Originally the "Makefile" was a link as in
ls ./ -l
lrwxrwxrwx 1 1133 543 13 Mar 18 Makefile -> build/Makefile
However now it is just a plain text file
ls ./ -l
-rw------- 1 11250 10513 14 Jul 6 Makefile
Somehow in the linux-windows-linux transference the link condition got lost
In my case, I have found the error in the title but not when doing make with a Makefile I suspect.
The error in the title specifies the name of the file in which the error is encountered: Makefile. Thus, your suspicion about "not when doing so with a Makefile" is unfounded. Although it is possible to run make without a makefile, and doing so can even be advantageous, make will always read a makefile if it can find one by one of the default names it looks for.
Moreover, though it may not be obvious in this case, the name given in the message is not just a base name but a (relative) path to the file. It is therefore complaining about a file named Makefile in make's working directory.
Right now there is a Makefile in the directory from where I call make
and it is like this
build/Makefile
no tabs or spaces I also did cat -A Makefile and I got
build/Makefileroot#themachine.....
Those two claims do not appear to be consistent with each other. In any case, however, neither one attributes valid makefile content to the makefile in question. This is likely the cause of the error message, which would then be a bit misleading.
It looks like you may be trying to have one makefile specify that another make be run in the build/ directory -- a so-called "recursive make". There are a couple of variations on how that is done, and they differ slightly in effect, but here's a guess at what you might be after for that top-level Makefile:
all:
$(MAKE) -C build
Of course, that second line needs to be indented with a leading tab, not spaces.
That will cause the top-level make run to trigger a second make run with the build/ directory as the second's working directory.
When compiling cross-compiler tool crosstool-0.43 (for arm9) on the CentOS 7.5 64-bit system, I encountered the following error：
cc -c -o flat_bl.o /home/muhuo/arm-linux-project/transplant-test/build-tools/crosstool-0.43/build/arm-9tdmi-linux/gcc-4.1.0-glibc-2.3.2/binutils-2.16.1/gprof/flat_bl.m
/home/muhuo/arm-linux-project/transplant-test/build-tools/crosstool-0.43/build/arm-9tdmi-linux/gcc-4.1.0-glibc-2.3.2/binutils-2.16.1/gprof/flat_bl.m:2:2: error: expected identifier or ??before ??token
% the percentage of the total running time of the
^
I don't know what the *. m file in binutils-2.16.1 is. Whether I need to install some other tools before?
From the picture above, Compiling *.m file with GCC should be wrong.
I need some help. Thanks.
The problem is that there is a builtin '.m.o' suffix rule which triggers with a higher priority than the '.c.o' suffix rule. There was an attempt to disable this rule under PR2587 but because it is an old-style suffix rule this doesn't work.
There are two possible solutions, one is to remove all builtin rules by adding the line .MAKEFLAGS: -r to binutils/gprof/Makefile.in somewhere, or else more correctly change the .SUFFIXES: line in the same file so that the '.m' comes after '.c', thus changing the rule priority.
Background
My current workflow to create/process markdown documents uses Sublime Text 2 with a Makefile build system, which calls pandoc to process them into PDF documents.
I've recently purchased a new mac, running OSX 10.8.5, and I've been running into some problems.
What's working:
I've installed Sublime Text 2, make (from xcode command line tools) and Pandoc (using the package on the website, as the cabal version wouldn't build for me).
What's not working:
When I try and build documents, it fails with the following error message from make:
pandoc -V geometry:margin=1in -S -o project_specification.pdf project_specification.markdown
make: pandoc: No such file or directory
[Finished in 0.0s with exit code 2]make: *** [project_specification.pdf] Error 1
The makefile however build absolutely fine if I run it using make at the terminal.
I think this is a problem with my path, however I'm really not sure how to set it. My understanding is that OSX has multiple paths for different applications (odd to me, as a Linux user until now), and I'm not sure how to set it for sublime to get it to work.
More background:
The makefile:
CPP_FILES = $(wildcard *.markdown)
OBJ_FILES = $(patsubst %.markdown,%.pdf,$(CPP_FILES))
%.pdf: %.markdown
pandoc -V geometry:margin=1in -S -o $# $(patsubst %.pdf,%.markdown,$#)
all: $(OBJ_FILES)
clean:
rm -f *.pdf
And finally:
I've found similar questions out there, but none with comprehensive answers, so I'm turning to stack overflow once again.
Thanks in advance for any help!
How about hack the path to wherever your pandoc is? Sublime Text 2 defaults to: /usr/bin:/bin:/usr/sbin:/sbin. This example is for a Tex Live installation using /usr/texbin, but you get the idea. There is one package that comes to mind that is more difficult to hack (e.g., Shell Turtlestein), but this works in general for most situations. I leave this running all the time when I load Sublime Text 2. If you need the turtle hack, just let me know. There are ways to adjust the path on a per package build script basis ( e.g., https://github.com/SublimeText/LaTeXTools/blob/master/LaTeX.sublime-build ), however, the following simplistic plugin usually works:
import os
LOCAL = '/usr/bin:/bin:/usr/sbin:/sbin:/usr/texbin:/usr/local/bin'
HOME = '/Users/HOME' ### !!! REPLACE WITH YOUR HOME PATH !!! ###
RVM = HOME + '/.rvm/bin:'
# Sublime's default path is
# /usr/bin:/bin:/usr/sbin:/sbin
os.environ['PATH'] += ':'
os.environ['PATH'] += LOCAL
os.environ['PATH'] += RVM
print 'PATH = ' + os.environ['PATH']
I have a Makefile similar to this:
.PRECIOUS: do/%.build
do/%.install: do/%.build
touch $#
do/%.build:
touch $#
My intention is that all do/.install targets depend on the do/.build target, and that the rule for the build target is run if the stamp file for the build target is missing, and that the install target is run if the build stamp is newer. This works fine during the first run:
$ make do/foo.install
touch do/foo.build
touch do/foo.install
It also works fine if the build stamp is newer:
$ touch do/foo.build
$ make do/foo.install
touch do/foo.install
However, it doesn't work as intended if the install stamp is present and the build stamp is missing:
$ rm do/foo.build
$ make do/foo.install
make: `do/foo.install' is up to date.
The install target is not run. What should I do? Does this have something to do with the fact that I have to add the .PRECIOUS line to avoid the automatic deletion of the build stamp?
Regards,
Tino
From the manual:
"If an ordinary file b does not exist, and make considers a target that depends on b, it invariably creates b and then updates the target from b. But if b is an intermediate file [i.e inferred from a pattern rule], then make can leave well enough alone. It won't bother updating b, or the ultimate target, unless some prerequisite of b is newer than that target or there is some other reason to update that target."
There are a couple of ways to solve this problem, but I know of no really clean way. Do any other targets depend on the build or install files?
I have a Makefile of the following content:
NUMBERS = 1 2 3 4
lib:
$(foreach var,$(NUMBERS),./a.out $(var);)
And this is the command that I run ( in the same directory as the Makefile)
make -f Makefile
But I got an error message saying that "The system cannot find the file specified".
Following the suggestion of one of the answers, I created the following file inside the same directory as the Makefile:
a.out
1.out
2.out
3.out
4.out
Now the error becomes:
./a.out 1; ./a.out 2; ./a.out 3;
./a.out 4; make (e=-1): Error -1 make:
*** [lib] Error -1
Note: I am running on Windows XP platform
The purpose of make is to create (and update) target files that depends on source files by running commands.
Here, the problem is with the command that is run. You are trying to run (through make) the command a.out but it does not exist, or is not an executable command. Try to replace a.out in your makefile by the actual executable command you want to run.
On Windows/DOS, use && instead of ; to join multiple commands on one line. You have to manually include a final command or the trailing && will throw a syntax error. Try something like:
NUMBERS = 1 2 3 4
lib:
$(foreach var,$(NUMBERS),.\a.out $(var) && ) echo.
It seems to me that the error comes because the file a.out cannot be located and not because the makefile could not be found.
Also if the name of your makefile is "Makefile" just invoking "make" is enough (without using -f option) as make by default would look for a file by names: GNUmakefile, makefile, and Makefile in that order.
Just what are you trying to do?
It seems to me that a plain script would be better suited rather than using make.
I found the answer by bta most useful, but it didn't work for me on both Windows and Linux, so I found a way to remove the final &&, which avoids the need for a no-op command that works on both platforms:
NUMBERS = 1 2 3 4
lib:
$(filter-out &&EOL, $(foreach var,$(NUMBERS), .\a.out $(var) &&)EOL)
Of course be careful of elements within your array matching &&EOL, but in my case, this isn't a problem.