Implementing bare-metal RISC-V on the Nexys-A7-100T FPGA [closed] - fpga

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I've recently taken up a project where I must implement a bare-metal RISC-V processor on the Nexys A7 100T FPGA board and run a simple hello world code on it.
However, I'm a bit new to RISC-V and have been struggling to get started with the bare-metal implementation. I've managed to implement RISC-V running on Debian Linux onto the board using the Github repository from Eugene Tarassov who is a principal engineer at Xilinx but this obviously did not meet the project specification since it's not bare-metal.
FPGA RISC-V SoC running Debian Linux: https://github.com/eugene-tarassov/vivado-risc-v#readme
I would greatly appreciate any books, online resources, tutorials or guidance that would help with this project. Thanks

Answer 1

For your hands-on check following github resources:
Rudi-RV32I
Picorv32
RISC-V microcontroller-like SoC (VHDL)
Nexys A7 port
"Hello world" example program
RISCV-Formal
Since you have asked for online resources check some of the following links:
RISCV Specifications
RISCV Technical Forums
RISCV Tech wiki
RISCV University Resources
From Custom CPU to Hello World in 30 Minutes
RISCV Publications
Book(s)
The RISC-V Reader: An Open Architecture Atlas
RISC-V Assembly Language
A general RISCV archive git page:
RISCV Archive