how to stop make -n from echoing same command multiple times - makefile

Question

I am using GNU make and have a Makefile which looks like this:
AB = A.txt B.txt
${AB}: makeAB.py
python makeAB.py
C.txt: ${AB} makeC.py
python makeC.py
When I type make -n C.txt, assuming makeAB.py needs to run, I get the output:
python makeAB.py
python makeAB.py
python makeC.py
Is there any way to write the Makefile so that the line python makeAB.py is not repeated? This is just a toy example, but in my actual application AB consists of many files, so I potentially get a whole screen of unnecessary output.
p.s. When called without -n, make (sensibly) only runs python makeAB.py once. So my problem is just with make -n.

Answer 1

The double output arises because the recipe is scheduled to run twice, once to build A.txt and again to build B.txt. This is normal behavior for make. In particular a rule such as your (as expanded) ...
A.txt B.txt: makeAB.py
python makeAB.py
... means that each of those two targets can be built via the associated recipe, not that a single execution of the recipe builds both (regardless of whether a single run does build both). It is 100% equivalent to:
A.txt: makeAB.py
python makeAB.py
B.txt: makeAB.py
python makeAB.py
When called without -n, make (sensibly) only runs python makeAB.py once. So my problem is just with make -n.
When you run with -n, make does not execute the recipe, so it cannot evaluate whether doing so to update (say) A.txt might also update B.txt. All it knows is that both targets are out of date, so it outputs the recipes that would be executed to update each one. This is completely sensible.
When you run make without -n, it has the opportunity to to observe that after updating one of A.txt and B.txt, the other is up to date. It might very naturally not even have noticed that the other was initially out of date. Having observed this, of course it does not execute the recipe again. The output would be clearer about what was happening if the recipe executions expressed which target was being built. For example, try this variation on the rule, which is more like how a multiple-target rule would ordinarily be written.
A.txt B.txt: makeAB.py
python makeAB.py $#
So, both make outputs are right in their own ways. Arguably, however, the makefile is wrong, because it does not capture the expectation and fact that running the recipe once would generate both outputs. This is a situation that the makefile language traditionally has difficulty expressing, and you will find other question about that here on SO and elsewhere.
If you are using a new enough version of GNU Make, then you can make use of its concept of "grouped target" rules, which addresses exactly this issue. By using &: as the separator in the first line of the rule, you communicate (only to pretty recent versions of GNU Make) that one execution of the rule creates all the designated targets. Example:
A.txt B.txt &: makeAB.py
python makeAB.py
Traditional makes and older GNU Make will just interpret the & as another target name. That means that those makes will accept such makefiles, but not behave the same as recent GNU make. Among other things, it means that if asked to build target &, they would try to do so, quite possibly with a surprising effect owing to the special significance of & to the shell.