I have a Makefile with 2 ifdef conditions that perform same action when that particular config is selected.
#ifdef A
//perform C
#endif /* A */
#ifdef B
//perform C
#endif /* B */
#ifdef A || B
//perform C
#endif
Last code block is not working. What is the right way to execute it in Makefile?
#ifdef and #endif are not make conditionals. You probably want:
ifdef A
# whatever if make variable A is defined
AB := defined
endif
ifdef B
# whatever if make variable B is defined
AB := defined
endif
ifeq ($(AB),defined)
# whatever if the make variable A or B is defined
endif
Note that ifdef A is not the same as ifneq ($(A),). So, if you want to test these variables not for definition but for emptiness, you probably want:
ifneq ($(A),)
# whatever if the value of make variable A is non-empty
endif
ifneq ($(B),)
# whatever if the value of make variable B is non-empty
endif
ifneq ($(A)$(B),)
# whatever if the value of make variable A or B is non-empty
endif
Here's one way to do it using a variant of the technique I proposed in a comment:
# De Morgan's Law: (!a && !b) == !(a || b)
ifndef A
ifndef B
NEITHER_A_NOR_B_DEFINED :=
endif
endif
ifndef NEITHER_A_NOR_B_DEFINED
# Perform C
endif
Related
I am trying to compile the source code twice with a MACRO defined & undefined. So for default the macro is undefined & i want to define this macro through arguments from Makefile, like
$(MAKE) -c $(present_dir)/new_dir -DONE_MACRO=1
so i am using this ONE_MACRO in file.h.
how this definition is reflected and knows to preprocessor. Here im using cygmake. How to pass an MACRO as argument to compiler with cygmake tool.
file.h:-
#if ONE_MACRO
#define some_targets
#else
#define other_targets
#endif
So how this ONE_MACRO is defined from make file, im trying to pass macro as argument as below
Makefile:-
MY_TARGET:
$(MAKE) -C $(present_dir)/target_dir -D ONE_MACRO=1 $(MAKECMDGOALS)
Here's an example of how to do what I think you want:
define_test.c:
#include <stdio.h>
#ifndef X
#define X 1
#endif
int
main()
{
printf("X = %d\n", X);
}
Makefile:
X = 1
CPPFLAGS += -DX=$(X)
define_test: FORCE
$(CC) $(CPPFLAGS) define_test.c -o $#
FORCE:
Then to pass a different value for macro X:
make X=2
(This assumes you want the value of the macro to be an integer; if you want the value to be a string, you have to get a bit more tricky with quoting properly.)
You can also add the definition directly to the CPPFLAGS, e.g.:
make CPPFLAGS+=-DX=2
For every compiler there is an environmental variable, which passes the areguments to compiler/linker. while dealing with other than GCC we need to find that environmental variables before usage.
like wise in my case RVCT31_CCOPT is the variable which passes the arguments to compiler while building.
I have some trouble with making Makefile. This is a part of Makefile.
dirs := fwd common bp bp_manager $(XRTE_HASH)
VPATH_ = $(foreach dir,$(dirs),$(SRCDIR)/$(dir))
INC_ = $(foreach dir,$(dirs),$(wildcard $(dir)/*.h))
CFLAGS_ = $(foreach dir,$(dirs),-I$(SRCDIR)/$(dir))
SRCS-y_ = $(foreach dir,$(dirs),$(notdir $(wildcard $(dir)/*.c)))
VPATH += $(VPATH_)
INC += $(INC_)
CFLAGS += $(CFLAGS_)
SRCS-y += $(SRCS-y_)
check:
echo $(CFLAGS)
echo $(SRCS-y)
VPATH and INC worked as I intended.
CFLAGS doesn't contain CFLAGS_
SRCS-y was printed as I inteded, but it has no effect when do "make" - SRCS-y_ was same with null.
CFLAGS and SRCS-y is okay when set manually (without function).
I thought Makefile is almost same with csh.
Can you explain me why the "make" ignores functions?
Thanks.
CFLAGS_ is just a string. $(CFLAGS_) is a variable's value. So you should have:
CFLAGS += $(CFLAGS_)
SRCS-y += $(SRCS-y_)
How do you define multiple variables using make's pattern specific variable values feature https://www.gnu.org/software/make/manual/html_node/Pattern_002dspecific.html#Pattern_002dspecific? For example, suppose that LIBDIR and RPATH have already been defined, and I want to set the following:
LDFLAGS += -L$(LIBDIR) $(RPATH)
LDLIBS += -lsomelibrary
for builds that match the pattern utest%. So for example,
utest% : -L$(LIBDIR) $(RPATH)
would get me halfway there, but then how to define the second variable?
I thought that maybe using multi-line variables https://www.gnu.org/software/make/manual/html_node/Multi_002dLine.html would work, but I can't quite get there. I've tried:
define linking_vars :=
LDFLAGS := -L$(LIBDIR) $(RPATH)
LDLIBS := -lsomelibrary
endef
utest% : $(linking_vars)
and also
define newline =
endef
utest_% : LDFLAGS := -L$(LIBDIR) $(RPATH) $(newline) LDLIBS := -lsomelibrary
but I haven't had any luck yet.
I'm not entirely sure I understand what you want to do, but it sounds as if this might do it:
utest% : LDFLAGS += -L$(LIBDIR) $(RPATH)
utest% : LDLIBS += -lsomelibrary
Is there a way to make GCC display the value of some preprocessed value during preprocessing? In particular, if I run the equivalent of:
gcc input.c -E >/dev/null
Is there a way to obtain the actual value of an expanded macro? Consider this example:
#if defined(A)
#define B bar
#else
#define B foo
#endif
#define XSTR(x) STR(x)
#define STR(x) #x
int main() {
#pragma message "B is " XSTR(B)
#error DIE
B a = 2;
return 0;
}
I would like to find out that B is foo in this case.
In my actual setup, I do not have access to the entirely preprocessed file, and I cannot remove the -E flag.
Rationale: I have a complex file setup with lots of syntax errors due to incorrectly defined macros, and the fastest way to debug it would be to use this #pragma/#error combination to find out the actual value, stop compilation, manually fix it, and run GCC again to find out where the next error will occur.
I am a newbie for Makefile. Optimizing my code Makefile code.
I have following code which is messy, Is there any better way of writing this.(for more clarity added space before each line)
ifdef X
ifndef Y
LNFLAGS + = -m32
else
ifndef Z
LNFLAGS + = -m32
endif
endif
endif