RISCV inline assembly compilation - gcc

To start with optimizing my code I have to start with adding assembly code into my C which is crosscompiled with gcc riscv toolchain, to start with I trying to implement simple riscv inline as follows
int src = 1;
int dst;
asm ("mov %1, %0\n\t"
"add $1, %0\n\t"
: "=r" (dst)
: "r" (src));
But error while crosscompiling it as
Error: unrecognized opcode `mov a1,a1'
Error: illegal operands `add $1,a1'
Should I add any specific flags for inline assembly implementation? any help would be great!

Related

how to let Inline assembly pass -O1 optimization

I have following dispatch code for my user level thread library.
The code can pass GCC and runs correctly without optimization, but if I choose -O1 optimization (also higher levels), when run the code, program generates segmentation fault.
Basically the function does save context and jump to next context.
void __attribute__ ((noinline)) __lwt_dispatch(lwt_context *curr, lwt_context *next)
{
__asm__ __volatile
(
"mov 0xc(%ebp),%eax\n\t"
"mov 0x4(%eax),%ecx\n\t"
"mov (%eax),%edx\n\t"
"mov 0x8(%ebp),%eax\n\t"
"add $0x4,%eax\n\t"
"mov 0x8(%ebp),%ebx\n\t"
"push %ebp\n\t"
"push %ebx\n\t"
"mov %esp,(%eax)\n\t"
"movl $return,(%ebx)\n\t"
"mov %ecx,%esp\n\t"
"jmp *%edx\n\t"
"return: pop %ebx\n\t"
"pop %ebp\n\t"
);
}
Thanks for help, I figured out some ways to solve it.
Normally compile this function as a separate .o file then use O3 to optimize it with other files.
using inline assembly is much easier and simpler than this function. Like below:
int foo = 10, bar = 15;
asm volatile("addl %%ebx,%%eax"
:"=a"(foo)
:"a"(foo), "b"(bar)
);
printf("foo+bar=%d\n", foo);
Another post has helped me figuring out labeling problem, see here: Labels in GCC inline assembly

Why cant seabios compile with -fno-inline

I'm trying to compile seabios in a more debug-able state, and so I want to cancel function inlining.
To do so, I have added -fon-inline to the compilation flag, but then I get compilation error:
error: can't find a register in class 'GENERAL_REGS' while reloading 'asm'
Which is complaning on the following code:
asm volatile(
"calll __call16big_from32"
: "+a" (callregs), "+m" (*callregs)
:
: "ebx", "ecx", "edx", "esi", "edi", "cc", "memory");
I've looked this error up and found this means that compiler has ran out of registers so it can't compile that asm statement.
The thing is, the exact same code compile just fine without -fon-inline, why is that?
Why doesn't compile?
The first argument to the asm may not share a register with the address of the second because the first is modified. If the function is inlined callregs may be a constant or an offset from the stack pointer, and therefore a separate register is not required.
How to fix the program so it compiles
Given the presence of volatile and "memory", and no reference to it the second argument may be removed.
asm volatile(
"call __call16big_from32"
: "+a" (callregs)
:
: "ebx", "ecx", "edx", "esi", "edi", "cc", "memory");

GCC inline assembly error: Error: junk `(%esp)' after expression

GCC inline assembly error: Error: junk `(%esp)' after expression
I'm studying gcc inline assembly. My environment is Win 7 32bit, mingw-gcc 4.6.1.
I have got a problem about the 'm' constraint. Here is my c function code:
static int asm_test(int a, int b)
{
int c = 0;
__asm__ __volatile__(".intel_syntax\n"
"mov eax, %1\n" //error
"mov edx, %2\n" //error
"add eax, edx\n"
"mov %0, eax\n" //error
".att_syntax"
:"=m"(c)\
:"m"(a),"m"(b)\
:"eax","edx"
);
return c;
}
For at&t code, it is like this:
static int asm_test(int a, int b)
{
int c = 0;
__asm__ __volatile__(
"movl %1, $eax\n" //error
"movl %2, $edx\n" //error
"addl $edx, $eax\n"
"movl $eax, %0\n" //error
:"=m"(c)\
:"m"(a),"m"(b)\
:"eax","edx"
);
return c;
}
For each of the three lines which operate input/output operands, gcc generate an error when compiling, read like this:
C:\Users\farta\AppData\Local\Temp\cc99HxYj.s:22: Error: junk `(%esp)' after expression
If i use 'r' for input/output constraint, the code will work. But I cannot understand why it works and what the error stands for. Can anyone tell me? As far as I know 'm' is just telling gcc not to allocate registers but directly access them in memory if inline asm code try to access input/output operands. Is this correct?
Thanks a lot.
The problem here is the GCC generates AT&T syntax construct for %0, %1 and %2. If you look at the generated assembly, it looks like:
.intel_syntax
mov eax, 8(%ebp)
mov edx, 12(%ebp)
add eax, edx
mov -4(%ebp), eax
which is not a valid Intel syntax.
Generally, you don't need to include in the inline assembly explicit load/store operation - just specify register constraint and the compiler will generate loads/stores by itself. This has the advantage that even if your variables (parameters, locals) do not reside in memory at all, but are in registers your code will still be correct - unlike in the case if you explicitly put memory load/stores there.
For your example, try the following code, look at the assembly (gcc -S) and notice how the compiler will perform moves from argument area (e.g. stack on x86) all by itself.
int asm_test(int a, int b)
{
__asm__ __volatile__ (
".intel_syntax\n"
"add %0, %1 \n"
".att_syntax \n"
:"+r"(a)
:"r"(b));
return a;
}

inline asm with gcc

I have this part of code that was compiling using ARMASM :
/* Software Interrupt */
/* we must save lr in case it is called from SVC mode */
#define ngARMSwi( code) __asm { SWI code,{},{},{lr} }
example of use :
ngARMSwi( 0x23);
I try to convert this to compile using gcc (code sourcery GCC-4.6.2 eabi). I found this link http://www.ethernut.de/en/documents/arm-inline-asm.html but I cannot find a way to compile this line correctly.
my best try is
#define ngARMSwi( code) __asm__ ("SWI " (code) : : :"lr" )
but I get compile error :
error: expected ':' or ')' before '(' token
Any help is appreciated!
You probably want
#define ngARMSwi(code) __asm__("SWI %0" : : "I"(code) : "lr")
Note that code is an input to the instruction, so it goes in the third section. Its place in the instuction is marked by the %0 in the string. The I is a constraint on code, indicating that it must be an 8-bit constant.

Use both SSE2 intrinsics and gcc inline assembler

I have tried to mix SSE2 intrinsics and inline assembler in gcc. But if I specify a variable as xmm0/register as input then in some cases I get a compiler error. Example:
#include <emmintrin.h>
int main() {
__m128i test = _mm_setzero_si128();
asm ("pxor %%xmm0, %%xmm0" : : "xmm0" (test) : );
}
When compiled with gcc version 4.6.1 I get:
>gcc asm_xmm.c
asm_xmm.c: In function ‘main’:
asm_xmm.c:10:3: error: matching constraint references invalid operand number
asm_xmm.c:7:5: error: matching constraint references invalid operand number
The strange thing is that in same cases where I have other input variables/registers then it suddenly works with xmm0 as input but not xmm1, etc. And in another case I was able to specify xmm0-xmm4 but not above. A little confused/frustrated about this :S
Thanks :)
You should let the compiler do the register assignment. Here's an example of pshufb (for gcc too old to have tmmintrin for SSSE3):
static inline __m128i __attribute__((always_inline))
_mm_shuffle_epi8(__m128i xmm, __m128i xmm_shuf)
{
__asm__("pshufb %1, %0" : "+x" (xmm) : "xm" (xmm_shuf));
return xmm;
}
Note the "x" qualifier on the arguments and simply %0 in the assembly itself, where the compiler will substitute in the register it selected.
Be careful to use the right modifiers. "+x" means xmm is both an input and an output parameter. If you are sloppy with these modifiers (eg using "=x" meaning output only when you needed "+x") you will run into cases where it sometimes works and sometimes doesn't.

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