Inferring BRAM on Intel Cyclone 10 LP - fpga

Question

I'm trying to port an HDL description of a regex coprocessor written for a Xilinx FPGA to a Cyclone 10 LP, to use it on the Arduino MKR Vidor 4000.
I have a problem with BRAM inference: I am trying to use the BRAM HDL description written for the Xilinx board (https://github.com/leonardo-panseri/cicero-on-vidor4000/blob/master/projects/cicero-cyclone/cicero-rtl/memories/bram.sv), but when I compile it with Quartus Prime Lite 21.1, it gets synthesized as logic instead of as memory blocks. I have even tried putting the Intel attribute 'ramstyle' to force the synthesis tool to correctly recognize it, but it seems to have no effects.
In the compilation log there are only two warning for the file, but they seem uncorrelated to my issue:
Warning (10230): Verilog HDL assignment warning at bram.sv(69): truncated value with size 32 to match size of target (1)
Warning (10268): Verilog HDL information at bram.sv(61): always construct contains both blocking and non-blocking assignments
The really strange thing is that in other places of the project the 'ramstyle' attribute does work, in fact the synthesis report for the RAM is as follows:
RAM Summary report for MKRVIDOR4000
Thu Jun 16 11:41:55 2022
Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis RAM Summary
----------------
; Legal Notice ;
----------------
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and other software and tools, and any partner logic
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; AXI_top:UIP|coprocessor_top:a_regex_coprocessor|topology_single:a_topology|engine_interfaced:anEngine|engine:anEngine|cache_block_directly_mapped_broadcast:a_cache|altsyncram:content_rtl_0|altsyncram_gll1:auto_generated|ALTSYNCRAM ; M9K ; Simple Dual Port ; 16 ; 48 ; 16 ; 48 ; 768 ; None ;
; AXI_top:UIP|coprocessor_top:a_regex_coprocessor|topology_single:a_topology|engine_interfaced:anEngine|engine:anEngine|fifo:gen_fifo[0].fifo_cc_id|altsyncram:content_rtl_0|altsyncram_sni1:auto_generated|ALTSYNCRAM ; M9K ; Simple Dual Port ; 32 ; 10 ; 32 ; 10 ; 320 ; None ;
; AXI_top:UIP|coprocessor_top:a_regex_coprocessor|topology_single:a_topology|engine_interfaced:anEngine|engine:anEngine|fifo:gen_fifo[1].fifo_cc_id|altsyncram:content_rtl_0|altsyncram_sni1:auto_generated|ALTSYNCRAM ; M9K ; Simple Dual Port ; 32 ; 10 ; 32 ; 10 ; 320 ; None ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+

Answer 1

The file linked to in the post, and the file the tool is warning about are not the same. The warnings in the posted refer to line numbers that are commented out in the linked file.
Also, the design uses % and / statements in code that changes on the fly which is not good practice in RTL.
if(w_valid) ram[w_addr / RATIO][w_addr % RATIO] <= w_data;
Recommend:
Double check you have the correct file as part of the build in the local project.
Remove the % and / operators from the RTL code that is changing on the fly. Its ok to use these for statements determined at elaboration time, its a better practice to not use them for dynamic code. Some exceptions can be a case where you know the results are on mod2 boundaries. For debugging 'why does this not infer RAM', remove them.
For RTL code which is not evaluated at compile-elaboration time:
When dividing is by 2^something, use shift operators rather than /.
When calculating the mod and the argument is mod 2^something, use the something number of LSBs of the argument as the mod, avoid the % operator.
When diving or getting the mod of something not a power of 2, synthesis does not handle the operation well in most cases.