I am trying to work with a Makefile that was created in the past. I have a line that I don't understand:
SUBDIRS = . src wsdl #SAMPLE_DIRS#
what is #SAMPLE_DIRS#?
Is that a variable exported from another file outside the Makefile?
Related
I want to create config file if it's missing out of template when I do make and then include it for further export of these variables. This code is working if .env file exist, however it doesn't if try to create this file inside this script. If I remove the last 2 lines from the script, the .env file is successfully copied.
ifndef ENV
override ENV = .env
endif
all:
ifneq (,$(wildcard $(ENV)))
$(info ************** Reading environment variables from $(ENV) **************)
else
$(warning !!!!!!!!!!!!! $(ENV) environmint config file is not found !!!!!!!!!!!!!)
$(info ************** Creating .env file and substitute variables **************)
cp $(CURDIR)/.env.example $(CURDIR)/.env
endif
include $(ENV)
export
I'm not entirely sure I understand the problem but I suspect you're just looking for a makefile rule that creates/updates $(ENV)...
$(ENV): $(CURDIR)/.env.example
cp $< $#
Edit: Some explanation as requested in the comments.
Although you refer to the file in question as a 'config' file, the fact that it's included in your makefile via...
include $(ENV)
means, of course, that it is in fact a makefile itself. That being the case this is covered by "How Makefiles Are Remade".
Basically, when make sees a file in an include directive it will look to see if it knows of any rules to update that file. If it does then it will invoke that rule before running the include directive. That way you can achieve a 'just-in-time' (sort of) update of the target in question.
I am trying to create makefile with sub-make files (library makefile, application makefile etc). But the repository where the makefile is located contain spaces in its path. e.g. /home/Khan/Project Khan/.../target. The space in between the "Project Khan" crashes the makefile and produces output.
OUTPUT: make*** No rule to make the target..
What should be done to execute the makefile successfully which have space in its PATH.
Many Thanks
I am writing a makefile script which should be able to parse a file which is created by the same makefile. I am using following code to parse $(FileName) file. When I execute I see **cat: InputFile:No such file or directory**. This code works fine for already existed file, but not working if file is not exist before I run make. Could you please suggest how can I resolve this issue? Thanks in advance.
Snippet from the Makefile -
test_connection:
. . .
//Create file named $(Filename)
. . .
$(call generate_list,$(FileName))
define generate_list
$(eval FILE_DATA= $(shell cat $(DIR)/$1); \
$(foreach word, $(FILE_DATA), \
. . .
endef
Your problem is that you are crossing boundaries. make parsing and processing happens before any rule bodies are run. target rule bodies are only run after that. So you can't create a file in a target rule body and expect it to be available for usage during make context (without using an included makefile but we'll get to that in a minute).
The simplest solution to this problem is simply to move the parsing out of make entirely and just do it in a shell (or other) script. This obviously doesn't work if you need the contents for some make-level decisions/etc. though.
The other possible solution is to use an included makefile and take advantage of the fact that when make rebuilds an included makefile it will restart its processing from the beginning (which then makes the contents of that makefile available from the start). To do this you would:
add an include $(Filename) line in your makefile
create a $(Filename): target with a rule to build it
parse the file (when it exists) in the top-level of your makefile
do what you need with the parsed data (in some makefile variables I assume) in the test_connection rule
In Gnumake, one can include a file as follows:
include some_file
I now wonder, is it possible to get the filepath of some_file from within that file, e.g. by doing $(shell pwd)? (I know that that command in particular doesn't work since it gets the path of the working directory, not the included file.)
You can use the MAKEFILE_LIST variable to obtain that. The last filename in that variable will be the current makefile, as long as you check it before you include any other files. Basically every time make reads a new makefile the name of that makefile is added to the end of the variable, but no value is ever removed from the variable even after the makefile is no longer being parsed:
THIS_MAKEFILE := $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))
I think you can use the readlink -f <file> command to get the path of the file. You just have to know from within the file what the filename is, which I'm assuming you can hardcode.
How would one test for the existence of files with a certain extension (.cpp in this case) in a directory at a specified location which is several directories down from the location of the makefile? I would like to print(echo) a message out if they are found
Your question is ambiguous. You mean, inside a make recipe you want to perform this test? If so then just write the appropriate shell scripting to check for the existence of said files.
If you mean outside of any recipe, in the makefile itself, if you're using GNU make you can use the $(wildcard ...) function:
ifneq (,$(wildcard some/sub/directory/*.cpp))
$(info found some cpp files!)
endif