Timing Summary:
Speed Grade: -1
Minimum period: 4.979ns (Maximum Frequency: 200.844MHz)
Minimum input arrival time before clock: 1.459ns
Maximum output required time after clock: 0.833ns
Maximum combinational path delay: No path found
This is obtained from xilinx 14.7 same cannot be found in xilinx vivado and by adding constraint wizard and calculating 1/(T-WNS ) = MAX Frequency is too low when compared with same programs in two different tool (but same hardware and same program)
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I have designed an algorithm-SHA3 algorithm in 2 ways - combinational
and sequential.
The sequential design that is with clock when synthesized giving design summary as
Minimum clock period 1.275 ns and Maximum frequency 784.129 MHz.
While the combinational one which is designed without clock and has been put between input and output registers is giving synthesis report as
Minimum clock period 1701.691 ns and Maximum frequency 0.588 MHz.
so i want to ask is it correct that combinational will have lesser frequency than sequential?
As far as theory is concerned combinational design should be faster than sequential. But the simulation results I m getting for sequential is after 30 clock cycles where as combinational there is no delay in the output as there is no clock. In this way combinational is faster as we are getting instant output but why frequency of operation of combinational one is lesser than sequential one. Why this design is slow can any one explain please?
The design has been simulated in Xilinx ISE
Now I have applied pipe-lining to the combinational logic by inserting the registers in between the 5 main blocks which are doing the computation. And these registers are controlled by clock so now this pipelined design is giving design summary as
clock period 1.575 ns and freq 634.924 MHz
Min period 1.718 ns and freq 581.937.
So now this 1.575 ns is the delay between any of the 2 registers , its not the propagation delay of entire algorithm so how can i calculate propagation delay of entire pipelined algorithm.
What you are seeing is pipelining and its performance benefits. The combinational circuit will cause each input to go through the propagation delays of the entire algorithm, which will take at up to 1701.691ns on the FPGA you are working with, because the slowest critical path in the combinational circuitry needed to calculate the result will take up to that long. Your simulator is not telling you everything, since a behavioral simulation will not show gate propagation delays. You'll just see the instant calculation of your combinational function in your simulation.
In the sequential design, you have multiple smaller steps, the slowest of which takes 1.275ns in the worst case. Each of those steps might be easier to place-and-route efficiently, meaning that you get overall better performance because of the improved routing of each step. However, you will need to wait 30 cycles for a result, simply because the steps are part of a synchronous pipeline. With the correct design, you could improve this and get one output per clock cycle, with a 30-cycle delay, by having a full pipeline and passing data through it at every clock cycle.
My design uses an Xilinx FPGA.
The synthesis report shows the following results:
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: 1.903ns
Maximum output required time after clock: 150.906ns
Maximum combinational path delay: 97.819ns
I do not know if I should use 150.906 ns or 97.819 ns to calculate throught.
What is maximum clock delay?
I havn't heard the term 'throught' with respect to circuit timing anytime before, but maybe my explanantion will give you the right hint.
At first, the maximum clock delay can be found in the Static Timing Report after Place & Route. But, this figure is mostly meaningless because one must also take the maximum data delay from any input or to any output into account. The result is already provided by the synthesis report. Please note, that this report only provides estimated results. Real results are only available from the Static Timing Report.
If you look for the maximum clock frequency (the inverse of the minimum clock period), then your synthesis report states, that your design does not include a path from one FF to another driven by the same clock ("Minimum period: No path found").
If you want to synchronously communicate with another IC on your PCB then the other 3 numbers are relevant. For example, the line "maximum output required time after clock" states that, all output signals are valid 151 ns after the clock signal toggles at the input pin (rising or falling edge depending on your design). If any of this outputs drive the inputs of another IC and if this IC is driven by the same clock source, then you must add the "minimum input arrival time" of this second IC (found in its data sheet). If this time is for example 49 ns then, the minimum period of your shared clock would be (your) 151 ns + 49 ns = 200 ns, that would be 5 MHz.
Same applies for the "minimum input arrival time before clock" of your FPGA design which must be added to the "maximum output required time" of the driving IC. If this time is for example 31 ns, then the minimum period of your shared clock would be 31 ns + (your) 2 ns = 33 ns, that would be 30 MHz.
In the same way, the "maximum combinational path delay" must be added to the "maximum output required time" of the IC which drives your inputs plus the "minimum input arrival time" of the IC your FPGA is driving. Given the same example figures from above, then the minimum period of your shared clock would be 31 ns + (your) 98 ns + 49 ns = 178 ns, that would be 5.6 MHz.
More details are explained in Xilinx Timing Constraint User Guide. Above, I explained the System Synchronous mode.
A more compact representation for Xilinx Vivado is given in Vivado Design Suite User Guide - Using Constraints.
There was also this presentation earlier available on the internet, but I didn't find the source PDF anymore.
I'm trying to synthetize any simple project in ISE for Spartan 6.
When I use Clocking Wizard for clk generator with f = 40 MHz (100Mhz external oscillator), XST says:
Timing Summary:
Speed Grade: -3
Minimum period: 9.482ns (Maximum Frequency: 105.458MHz)
Minimum input arrival time before clock: 2.623ns
Maximum output required time after clock: 3.597ns
Maximum combinational path delay: 5.194ns
OK, but when I change clk frequency in core generator to 100MHz, the response is Maximum Frequency is about 47MHz ...
What is wrong?
What is the right way to determine max frequency?
The reported maximum frequency in synthesis is only a rough estimation based on fanout, LUT levels, i/o-buffers, ...
The real timing analysis is done after Place & Route.
I have a project which already utilizes synthesis timing constraints (additional xcf-file), were XST reports f_max = 82 MHz. After P&R the design achieves 152 MHz :)
I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.
A pure Verilog solution is not stable, so dedicated FPGA resources must be used.
Please see this previous answer; it applies to Verilog also, even through tagged VHDL.
My spartan 3a fpga board has a 50mhz clock while implementing a microblaze with ram ddr2 , it required a frequency of 62mhz which was edited by my program , when asked about this , they told me that 60mhz clock is used to generate other clocks internally but how does a 50mhz clock produce a 62mhz clock which is higher !?
in Xilinx Spartan devices you can use so called DCMs (digital clock managers) that give you a whole lot of possibilities; see Spartan User Guide or Xilinx Spartan 3 DCM. with the synthesizer option, clock multiplication/division is possible.
There are built in technologies that multiply the clock to higher frequencies. See Frequency Multiplier and Phase Locked Loop
under your design name in Implementation window in ISE right click and add new sorce select IPcore then select clocking wizard you can enter the primary freq : 50 mhz and required out freq: 62 mhz and the core generator will do it for you.