I want to create a makefile that syncs files from a server to my local PC. With this makefile I want to only copy from my server to my local computer those files that were modified. To do that I did a makefile based in boths answers from here and here. This is my code:
#!/usr/bin/make -f
FILES = *.csv
SCP = scp id#server:~/Results
LAST_SYNC = .last_sync
.PHONY: sync
sync : $(LAST_SYNC)
$(LAST_SYNC) : $(FILES)
$(SCP) $?
touch $(LAST_SYNC)
If I run make it appears the following error:
make: *** No rule to make target '*.csv', needed by '.last_sync'. Stop.
Are there any way to solve this problem?
EDIT:
I've just changed the problem with the FILES variable according to G.M.'s suggestion:
FILES := $(wildcard *.csv)
Now the following error appears:
scp id#server:~/Results results1.csv results2.csv results3.csv
results3.csv: Not a directory
make: *** [Makefile:13: .last_sync] Error 1
Related
Compile this driver with:
echo "obj-m := tiny_i2c_adap.o" > Makefile
make -C SUBDIRS=$PWD modules
Makefile:
obj-m := tiny_i2c_adap.o
Error :
prashanth#prashanth-Lenovo-ideapad-520-15IKB:~$ make -C /usr/src/linux-headers-$(uname -r) M=$PWD modules
make: Entering directory '/usr/src/linux-headers-5.1.7-050107-generic'
make[1]: * No rule to make target '/home/prashanth/tiny_i2c_adap.c', needed by '/home/prashanth/tiny_i2c_adap.o'. Stop.
Makefile:1571: recipe for target 'module/home/prashanth' failed
make: * [module/home/prashanth] Error 2
make: Leaving directory '/usr/src/linux-headers-5.1.7-050107-generic'
Remember $PWD is a shell variable, which contains the current working directory. So when you run:
~$ make -C /usr/src/linux-headers-$(uname -r) M=$PWD modules
the value of $PWD here is the directory you are in when you run make (in this case your home directory) so you're running:
~$ make -C /usr/src/linux-headers-$(uname -r) M=/home/prashanth modules
So the kernel makefile assumes that your module lives in /home/prashanth because that's where you set the M variable to.
You need to either use the correct path for M, or else use cd to switch to the directory containing your source before invoking make so that $PWD will contain the right path.
I am trying to run build with some new changes in makefile where new folder needs to be created and place some files in that folder.
Here is my target placed in my make file:
tools_mvv32: $(RELEASE_FILES) ## Which has files pointing to TGTTEST32
define file_copy
mkdir -p $(#D)
cp -f $< $#
endef
TGTTEST32 := /home_test/workspace/copy/limited_projects/src/main/scp/build/Linux/project/primary/ktl
$(TGTTEST32)/tools/bin/%: $(TGTTEST32)/bin/%
$(file_copy)
When i try to run build by placing the target i.e. with specific file name with hardcoded as follows, It works fine
/home_test/workspace/copy/limited_projects/src/main/scp/build/Linux/project/primary/ktl/tools/bin/mpf: /home_test/workspace/copy/limited_projects/src/main/scp/build/Linux/project/primary/ktl/bin/mpf
$(file_copy)
May i know if any syntax is incorrect in my generic target ?
I am hitting below issue with my generic target:
gmake: *** No rule to make target /home_test/workspace/copy/limited_projects/src/main/scp/build/Linux/project/primary/ktl/tools/mpf
This seems slightly related to How to write Makefile where target and source files have the same extension?. In that question the extensions are the same, but the input and output files seem to be in the same directory and filenames are being conditionally renamed.
I have a large collection of .txt files in ../src/ that need to be processed, and dumped into ./ (which is a directory called target/) as txt files of the same name. I want to use make, so that only files in ../src/ that have been changed get updated in ./. I would like to get the prototype working before I put the real code in.
My Makefile in ./ is as follows:
DIR = ../src
INPUTS = $(wildcard $(DIR)/*.txt)
OUTPUTS = $(patsubst $(DIR)/%.txt,%.txt,$(INPUTS))
all: $(OUTPUTS)
.PHONY: $(INPUTS)
check:
#echo "DIR = $(DIR)"
#echo "INPUTS = $(INPUTS)"
#echo "OUTPUTS = $(OUTPUTS)"
%.txt: $(DIR)/%.txt
sed -e "s/test/cat/g" "$<" > $#
For now, the contents of ../src/ are test1.txt and test2.txt.
As the Makefile stands now, running make test2.txt generates the file as expected.
target/ $ make test2.txt
sed -e "s/test/cat/g" "../src/test2.txt" > test2.txt
Running make check shows the INPUTS and OUTPUTS correctly.
target/ $ make check
DIR = ../src
INPUTS = ../src/test1.txt ../src/test2.txt
OUTPUTS = test1.txt test2.txt
If I run make all, it generates every file, every time. This is expected with the .PHONY $(INPUTS) line in there.
If I remove the .PHONY $(INPUTS) target, Make gets all bound up in itself trying to find the target to make ../src/test1.txt and keeps prefixing $(DIR) in front of it until it makes too long of a filename and gives up.
make: stat: ../src/../src/../src/ [repeat for a few pages] ../src/../src/test1.txt: File name too long
make: stat: ../src/../src/../src/ [repeat for a few pages] ../src/../src/../src/test1.txt: File name too long
make: *** No rule to make target `../src/../src/../src/[repeat]../src/../src/test1.txt', needed by `../src/[repeat]../src/../src/test1.txt'. Stop.
It never does get to processing test2.txt.
As I was drafting this, I had the idea to remove the ../ from the DIR,
and relocate the Makefile so it was parent to both src/ and target/. That approach seems to work, but isn't ideal. Eventually there would be a chain of these Makefiles, each pulling from one directory to another.
Is there a way to keep the Makefile in 'target/' along with the generated destination files, and base those destination files off of something in a relative path?
Replace
%.txt: $(DIR)/%.txt
with:
${CURDIR}/%.txt: $(DIR)/%.txt
This way %.txt does not match any .txt file in any directory. In other words, you limit this rule's scope to files in ${CURDIR}/ only and this prevents that endless recursion.
See ยง10.5.4 How Patterns Match for more details.
It is also good practice to avoid relative paths:
DIR = $(abspath ../src)
I have two GNUmakefiles in my directory as follows,
GNUmakefile &
GNUmakefile2
Could someone please let me know the command I have to use, if I have to let the "make" command to process "GNUmakefile2" instead of "GNUmakefile".
I used the below command,
make -f GNUmakefile2
but in that case, I am getting the following errors,
This is gnustep-make 2.6.1. Type 'make print-gnustep-make-help' for help.
make[1]: ** No rule to make target `internal-master-tool-all'. Stop.*
make: ** [internal-all] Error 2*
I think it is considering GNUmakefile as makefile (when I use make with -f command), so it is checking for rules in GNUmakefile.
At present what I am doing is I am renaming the required file (which I want, make command to execute) to "GNUmakefile". And I am not getting any errors while executing "make" command, but I don't think this is the correct solution.
Please let me know which command I need to use for this scenario. Thanks for your help.
After checking Beta's solution (i.e.,but that makefile is invoking Make a second time, and the second Make process is probably reading GNUmakefile) what I have done is I renamed existing "GNUmakefile" to "GNUmakefile3".
So at present in my directory the following makefiles are present:- "GNUmakefile2" & "GNUmakefile3".
And then I executed the following command:- $ make -f GNUmakefile2
I recieved the below errors,
This is gnustep-make 2.6.1. Type 'make print-gnustep-make-help' for help.
make[1]: GNUmakefile: No such file or directory
make[1]: * No rule to make target `GNUmakefile'. Stop.
make: * [internal-all] Error 2
Please let me know what is the problem here
Your makefile includes two huge makefiles from the FSF. The second, library.make, contains this rule:
ifeq ($(GNUSTEP_MAKE_PARALLEL_BUILDING), no)
# Standard building
...
else
# Parallel building. ...
internal-library-all_:: $(GNUSTEP_OBJ_INSTANCE_DIR) $(OBJ_DIRS_TO_CREATE)
$(ECHO_NOTHING_RECURSIVE_MAKE)$(MAKE) -f $(MAKEFILE_NAME) ...
endif
and the first, common.make contains this assignment:
# The default name of the makefile to be used in recursive invocations of make
ifeq ($(MAKEFILE_NAME),)
MAKEFILE_NAME = GNUmakefile
endif
So try either make -f GNUmakefile2 GNUSTEP_MAKE_PARALLEL_BUILDING=no or make -f GNUmakefile2 MAKEFILE_NAME=GNUmakefile2, and see if that solves the problem.
I need a variable in makefile that can be shared across subdir makefiles ( recursive build strategy), and finally use it for some decision making. I had earlier thought export is the way to do it, but I am not getting desired results.
following are my makefiles:-
Target.mk (common include for both Makefile.mk & Subdir.mk)
Makefile.mk
Subdir.mk
FILE : Target.mk
export TARGET_PROPERTIES :=
FILE : Makefile.mk
-include Target.mk
.PHONY : all
all :
$(MAKE) -C $(PWD) -f Subdir.mk all
#echo "#------------------------------------------------------------#"
#echo "Target build properties"
#echo $(TARGET_PROPERTIES)
#echo "#------------------------------------------------------------#"
FILE : Subdir.mk
-include Target.mk
TARGET_PROPERTIES+=alpha
TARGET_PROPERTIES+=beta
$(warning $(TARGET_PROPERTIES))
all:
#echo "Subdir.mk......[OK]"
PROBLEM:-
I want TARGET_PROPERTIES, to be updated from Subdir.mk and the use the results in Makefile.mk
following is my output
$ make -f Makefile.mk
make -C /cygdrive/c/make_pf -f Subdir.mk all
make[1]: Entering directory `/cygdrive/c/make_pf'
Subdir.mk:8: alpha beta
Subdir.mk......[OK]
make[1]: Leaving directory `/cygdrive/c/make_pf'
#------------------------------------------------------------#
Target build properties
#------------------------------------------------------------#
in Subdir.mk TARGET_PROPERTIE updates, fine until here.
Subdir.mk:8: alpha beta
in Makefile.mk after return from "Subdir.mk - all target" it resets to NULL.
Not sure what I am doing wrong
P.S. I am using cygwin environment.
Exported environment variables are copied to child processes, so changes there do not propagate back into the parent process.
Your best bet would probably to avoid recursive makefiles and instead include everything from the main Makefile.mk. Google for Recursive Make considered harmful for pointers how to do this.