What will happen if I read and write a register both at the posedge of the clock cycle? I encountered this question while learning a RISC-V pipeline implementation which uses the technique called double bump to avoid this question. I wonder why this is necessary to split the write and read of an register.
Already solved. Because 5-stages pipeline I designed launch instruction at posedge, and at negedge the result in the WT stage can be read into register file. Thus it is just a way to save a stall. I misunderstood that at first.
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Is it possible to use digitalRead() function on Arduino setup to check if a circuit is opened or closed and act as a physical DEBUG flag?
Yes, you can. Do a pinmode() first - maybe you need to set the pull-up. Maybe wait a tiny bit for the levels to settle down, since you probably just turned it on. Then you can read the pin with digitalRead().
I'm currently analyzing a given FPGA Verilog program and I stumbled upon the lpm_constant IP-Core, provided by Altera.
The only thing it does is to provide a constant value to a bus.
My Question is, why one should use this IP-Core, instead of a wire with constant value, or a reg with initialization in initial block, or reset cycle.
I also don't see the point of the reason being either to improve performance (Fitter should take care of this anyways, regardless of implementation) or compatibility with other designs (the language Verilog/VHDL is standardized, so why would this be an issue).
Thanks for clarification.
One can use the In-System Memory Content editor to change the value of the "constant" at design run time, to help in debug and testing of the design. We lose this capability if we hard code a value in RTL.
As #JHBonarius said the only reason to use lpm_constant (Altera Megafunction) if you describe your project in a schematic way, i.e. use Block Design File (*.bdf). If you use HDL-like approach use CONSTANT to make code CAD Tools independent.
This is a question inspired by this question and answer pair: call questa sim commands from SystemVerilog test bench
The questions asks how Verilog code could control the executing simulator (QuestaSim). I saw similar questions and approaches for VHDL, too.
So my question is:
Why should a simulation (slave) have power of its simulator (master)?
What are typical use cases?
Further reading:
call questa sim commands from SystemVerilog test bench
VerTcl - A Tcl interpreter implemented in VHDL
Why? Can anyone answer "why"? Well, perhaps the product engineer, or developer at Mentor that drove the creation of such behavior can answer that. But lacking that, we can only guess. And that's what I'm doing here.
I can think of a few possible use cases, but they aren't something that cannot be done in another manner. For example, one could have a generic "testbench controller" that depending on generics/parameters could invoke certain simulator behavior. (Edit: After re-reading one of your links, I see that's the exact use case.)
For example, say I have this "generic" testbench code as:
module testbench;
parameter LOG_SIGNALS = 1'b0;
initial
begin
if LOG_SIGNALS
begin
// Log all signals in the design
mti_fli::mti_Cmd("add wave -r /*")
end
endmodule
Then, one could invoke this as:
vsim -c -gLOG_SIGNALS=1 work.testbench
The biggest use case for this might be if vsim is invoked from some environment. If one were to do a do file, I'm not sure one can pass parameters to the script. Say one had the following do file:
if {$log_signals} {
add wave -r /*
}
How does one set $log_signals from the command line? I suppose one could do that through environment variables, such as:
if { [info exists ::env(LOG_SIGNALS)] } {
add wave -r /*
}
Other uses cases might be to turn on/off the capturing of coverage data, list files, maybe even a quirky case of ending simulation.
But of course, all of these can be handled in other manners. And in manners I think are much more clear and much easier to maintain.
As for VerTCL, I find it fascinating. But incomplete. Or at very least barebones. I find scripted testenches exceedingly useful (we use them where I work). And VerTCL is a great way to do it (if you like TCL). But it does need some framework around it to read signals, drive signals, and otherwise manage a simulation.
Ideally, you wouldn't need a simulator API if the HDL was comprehensive enough to do all the functions that are currently left to the simulator. At its inception, Verilog was implemented as an interpreted language and the command line was the Verilog language instead of some other command line interface we see today based on Tcl.
But as simulators became more complex, they needed commands that interacted with the file system, platform, OS, as well as other features at faster pace than the HDL standard could keep up with. The IEEE HDL standards stop at any implementation specific details.
So simulation tool vendors developed command line interfaces (CLI) to meet user needs for debugging and analysis. These CLIs are robust enough to create stimulus and check behaviors that there can be an overlap in functionality of the CLI code versus what's in your testbench source code. So having an API to your simulators CLI can make it easier to control the flow of commands to the simulator and avoid duplication of procedures.
For example, maybe you want to start logging signals to add to a waveform after the design gets out of reset. From the CLI, you would have to set a watch condition on the reset signal that executes the logging command when reset goes inactive. Using the simulator API, you could just put that command in your bench in the spot in your where release reset.
All the codes I've found generate me some errors. My FPGA manufacturer FIFO's when I try to read and write at the same time it create me problems in simulation and also I can't modify it or adapt to another FPGA.
Can someone advice me an already written Asynchronous FIFO (2 Clock FIFO) code in VHDL, possibly already used without problems?
I need the possibilty to read and write at the same time with 2 different clocks.
Our PoC Library has a cross-clock FIFO called PoC.fifo.ic_got. (ic = independent clocks)
This FIFO can be configured in size and width. You can also chose to synthesize it with LUT-RAM or BlockRAM/altsyncram. Depending on the chosen vendor settings, it will use device specific code to improve carry-chain mapping or otherwise use a generic description.
This FIFO requires other modules and packages from PoC Library like PoC.utils, PoC.mem.ocram.* or PoC.arith.counter_gray.
This FIFO was tested on several devices:
Altera: Cyclone III, Startix-II/IV
Xilinx: Spartan-3, Virtex-5/6/7, Kintex-7
Feel free to test it on other devices :).
I am using tetramax to measure the fault coverage of some test-benches.
I am running the test-benches and dumping on a VCD file input and output of the core I want to test.
The clock as well as the reset are already managed by my external testbench.
I guess that therefore I do not need to add clock and reset in my Tetramax script.
I do not know however if specifying the clock has any side effect.... for instance in some internal delay computation between input and output.
Does anyone have more information about the effect of adding clock and reset in a tetramax script?
Cheers,
The clock as well as the reset are already managed by my external testbench. I guess that therefore I do not need to add clock and reset in my Tetramax script.
Wrong! You need to tell it which signal is the clock and which is the reset as these are special signals it needs to know about. It doesn't matter what your test-bench does. It shouldn't even be loaded.
Tetramax needs to know how to control the flip-flops in the design. Part of this is knowing how to reset them and clock them. When you specify the clock and reset it tells Tetramax how to do this. It needs to know this to generate or simulate test patterns. If you don't give it this information it can't do anything, or rather it's limited to testing things which don't involve flip-flops (which isn't much).
You'll also need to tell it about any test control signals that have to be enabled in order to enable test modes, scan chains, etc.