I try to write VHDL code in Vivado to show multiply 8 bit number by 1,2,3,4.
i got the error in line (y <= ..) :
" width mismatch in assignment; target has 10 bits, source has 8 bits error in vhdl"
i dont understand whats the problem
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std;
use IEEE.STD_LOGIC_unsigned.ALL;
entity multiplies is
Port ( sel : in STD_LOGIC_vector (1 downto 0);
x : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (9 downto 0));
end multiplies;
architecture Behavioral of multiplies is
component multi
port (i0: in std_logic_vector(9 downto 0);
X : in std_logic_vector(9 downto 0);
z: in std_logic_vector(9 downto 0));
END COMPONENT;
signal A2: std_logic_vector(9 downto 0);
signal A3: std_logic_vector(9 downto 0);
signal A4: std_logic_vector(9 downto 0);
begin
with sel select
Y<= (x) when "00",
A2 when "01",
A3 when "10",
A4 when others;
end Behavioral;
Port x is 7:0 whereas port y is 9:0.
So you can't assign x to y directly in your with-select clause, you correctly get an error.
That part of the clause can instead be:
Y <= "00" & x when "00",
A2 when "01",
A3 when "10",
A4 when others;
Related
My code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.costanti.all;
entity Multiplier is
generic(nbA:integer:=nbA;
nbB:integer:=nbB);
port (
A: in STD_LOGIC_VECTOR(nbA-1 downto 0);
B: in STD_LOGIC_VECTOR(nbB-1 downto 0);
clk: in STD_LOGIC;
R: out STD_LOGIC_VECTOR(nbA+nbB-1 downto 0));
end Multiplier;
architecture Behavioral of Multiplier is
component AdderTree is
generic(nbit: integer:=nbA+nbB);
port (
IN1: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN2: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN3: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN4: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN5: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN6: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN7: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN8: in STD_LOGIC_VECTOR(nbit-1 downto 0);
IN9: in STD_LOGIC_VECTOR(nbit-1 downto 0);
S: out STD_LOGIC_VECTOR(nbit-1 downto 0)
);
end component;
signal V : STD_LOGIC_VECTOR(nbA-1 downto 0);
signal P : STD_LOGIC_VECTOR((nbA*nbB)-1 downto 0);
signal PP_0to6 : STD_LOGIC_VECTOR( (nbA)+(nbA+1)+(nbA+2)+(nbA+3)+(nbA+4)+(nbA+5)+(nbA+6)-1 downto 0); --(dim(pp0+PP1+PP2+PP3+PP4+PP5+PP6) downto 0 )
signal PP7 : STD_LOGIC_VECTOR(nbA+nbB-1 downto 0);
signal P7 : STD_LOGIC_VECTOR(nbA downto 0);
signal PPP : STD_LOGIC_VECTOR((nbA+nbB)*(nbB+1)-1 downto 0);
begin
for_g: for i in 0 to nbB-1 generate
V <= (others => B(i));
P((nbB)*(i)+(nbB-1) downto (nbB)*(i)) <= V and A;
end generate for_g;
P7 <= '0' & P((nbA*nbB)-1 downto (nbA*nbB)-1-(nbB-1));
PP_0to6(nbB-1 downto 0) <= P(nbB-1 downto 0); --PP0
for_g2: for i in 0 to nbB-3 generate
PP_0to6((nbB+1)*(i+1)+(i*(i+1)/2)+7 downto (nbB+1)*(i+1)+(i*(i+1)/2)) <= P(nbB*(i+1)+(nbB-1) downto nbB*(i+1)); --PP1 to PP6
PP_0to6((nbB+1)*(i+1)+(i*(i+1)/2)-1 downto (nbB+1)*(i)+((i-1)*(i)/2)+7+1) <= (others => '0');
end generate for_g2;
PP7(nbA+nbB-1 downto nbA-1) <= P7;
PP7(nbA-2 downto 0) <= (others => '0');
PPP_0to6: for i in 3 to nbB-2 generate
PPP(((i+1)*(nbA+nbB-1)+i)-(8-i) downto i*(nbA+nbB)) <= PP_0to6( (i+1)*(nbB-1)+((1/2)*((i*i)+(3*i))) downto i*(nbB)+(i-1)*i/2); --PP0 to PP6
PPP(((i+1)*(nbA+nbB-1)+i) downto ((i+1)*(nbA+nbB-1)+i)-(8-i)+1)<= (others => '0');
end generate PPP_0to6;
-- Fill last 32 bits of PPP
--Insert ADDER TREE
end Behavioral;
Portion of the error code: portion of code
PPP_0to6: for i in 0 to nbB-2 generate
PPP(((i+1)*(nbA+nbB-1)+i)-(8-i) downto i*(nbA+nbB)) <= PP_0to6( (i+1)*(nbB-1)+((1/2)*((i*i)+(3*i))) downto i*(nbB)+(i-1)*i/2); --PP0 to PP6
PPP(((i+1)*(nbA+nbB-1)+i) downto ((i+1)*(nbA+nbB-1)+i)-(8-i)+1)<= (others => '0');
end generate PPP_0to6;
Hi, I'm making a multiplier on vhdl, but on line 66 it reports me the following error:
if i=1: [Synth 8-690] width mismatch in assignment; target has 9 bits, source has 7 bits ["...Multiplier.vhd":66]
if i=2: [Synth 8-690] width mismatch in assignment; target has 10 bits, source has 5 bits ["...Multiplier.vhd":66]
if i=3: [Synth 8-690] width mismatch in assignment; target has 11 bits, source has 2 bits ["...Multiplier.vhd":66]
and so on..
I can't understand why, they seem to be the same size ..
my constant are:
nbA=8
nbB=8
and the signal P, PP_0to6 and PPP:
signal P : STD_LOGIC_VECTOR((nbA*nbB)-1 downto 0);
signal PP_0to6 : STD_LOGIC_VECTOR( (nbA)+(nbA+1)+(nbA+2)+(nbA+3)+(nbA+4)+(nbA+5)+(nbA+6)-1 downto 0);
signal PPP : STD_LOGIC_VECTOR((nbA+nbB)*(nbB+1)-1 downto 0);
N.B. I make sure to shift to the rigth by adding zeros as in the figure:
schema
The error is here:
PPP(((i+1)*(nbA+nbB-1)+i)-(8-i) downto i*(nbA+nbB)) <= PP_0to6( (i+1)*(nbB-1)+((1/2)*((i*i)+(3*i))) downto i*(nbB)+(i-1)*i/2);
but if I tried to replace the value of i:
i=0: PPP(7 downto 0) <= PP_0to6(7 downto 0);
i=1: PPP(24 downto 16)<=PP_0to6(16 downto 8)
i=2: PPP(41 downto 32)<=PP_0to6(26 downto 17)
i=3: PPP(58 downto 48)<=PP_0to6(37 downto 27)
...
...
the dimensions look the same.
I guess strictly speaking this answer doesn't really answer your question, since I'm not trying to figure out where your error is. But I'm convinced that if you change your coding style you won't encounter such difficult to debug errors any more.
As mentioned in my comments, your code will become must clearer and easier to debug if you split the signal up properly. I.e. don't create one giant signal for everything.
VHDL has arrays and records, use them, they won't make your circuit any larger, but the code will be much easier to reason about.
It's been a while since I actually wrote VHDL, so the syntax below might contain typo's, but hopefully the idea behind the code is clear:
constant c_AllZeros : std_logic_vector(c_MaxZeros - 1 downto 0) := (others => '0');
...
type t_P is std_logic_vector(c_SomeLength - 1 downto 0);
subtype t_P_Array is array (natural range <>) of t_P;
...
signal P : t_P_Array(0 to c_NumInputs - 1);
...
PPP_0to6: for i in PPP'range generate
PP(i) <= P(i) & c_AllZeros(index downto 0);
PPP(i) <= c_AllZeros(c_MaxZeros - index downto 0) & PP(i);
end generate PPP_0to6;
As you might notice, I also got rid of the explicit indices for the for-loop in the generate. There's still a magic number when indexing the all_zeroes signal to generate PPP. If I was writing this code, I'd replace that with some (calculated) constant with a meaningful name. This will make the code both more readable and trivial to change later on.
Note that there's other ways to do this. E.g. you could first set all bits of all PP signals to 0 and then assign a slice of them the P value.
I know a little bit of VHDL.
My goal is to have a 4 bit vector input and sending an output to a 7 segment display at base4 number.
e.g. 1111->33, 1001->21
I am struggling with the conversion from base2 to base4 numbers in VHDL. As previously stated, when I have converted base2 to base4 I want to send it to a 7 segment display, please could you advise me how to do this?
Binary is easy to convert to any power-of-2-based number system like 4 or 8 or 16. Just group bits by log2(bigger base). In case of base 4 group them by log2(4)=2:
00->0
01->1
10->2
11->3
1110->32
You simply split vector of length X to X/2 vectors of lengths 2 each by connecting wires:
library IEEE;
use IEEE.std_logic_1164.all;
-- 8 binary bit number to 4 base4 numbers
-- binary - is input number
-- d1 is the most significant base-4 digit
-- ...
-- d4 is the least significant base-4 digit
entity BinToBase4 is
port(binary : in STD_LOGIC_VECTOR(7 downto 0);
d1 : out STD_LOGIC_VECTOR(1 downto 0);
d2 : out STD_LOGIC_VECTOR(1 downto 0);
d3 : out STD_LOGIC_VECTOR(1 downto 0);
d4 : out STD_LOGIC_VECTOR(1 downto 0)
);
end BinTobase4;
architecture rtl of BinToBase4 is
begin
d1 <= binary(7 downto 6);
d2 <= binary(5 downto 4);
d3 <= binary(3 downto 2);
d4 <= binary(1 downto 0);
end rtl;
Testbench for this:
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component BinToBase4 is
port(
binary : in STD_LOGIC_VECTOR(7 downto 0);
d1 : out STD_LOGIC_VECTOR(1 downto 0);
d2 : out STD_LOGIC_VECTOR(1 downto 0);
d3 : out STD_LOGIC_VECTOR(1 downto 0);
d4 : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
signal num : std_logic_vector(7 downto 0);
signal d1 : std_logic_vector(1 downto 0);
signal d2 : std_logic_vector(1 downto 0);
signal d3 : std_logic_vector(1 downto 0);
signal d4 : std_logic_vector(1 downto 0);
begin
b4: BinToBase4 port map(num,d1,d2,d3,d4);
process
begin
num <= "10110001";
wait for 1 ns;
assert(d1="10") report "Fail 10" severity error;
assert(d2="11") report "Fail 11" severity error;
assert(d3="00") report "Fail 00" severity error;
assert(d4="01") report "Fail 01" severity error;
wait;
end process;
end tb;
You may want to extend d1, d2, d3, d4 to four bits to connect them directly to 7-segment display. Use concatenation &:
d1 <= "00" & binary(7 downto 6);
d2 <= "00" & binary(5 downto 4);
d3 <= "00" & binary(3 downto 2);
d4 <= "00" & binary(1 downto 0);
just don't forget to adjust vector sizes accordingly.
I.e. dx would become...
signal dx : std_logic_vector(3 downto 0);
Unlike most counters that i have viewed on this website, my BCD counter requires the use of two 4-Bit adders in order to make 1 8-Bit BCD counter. What I have done so far is design a regular full adder, used that to design a regular 4 bit adder.
This is my code so far:
library ieee;
use ieee.std_logic_1164.all;
entity adder8b_custom is
port(
X: in std_logic_vector( 7 downto 0);
Y: in std_logic_vector (7 downto 0);
S: out std_logic_vector (7 downto 0));
end adder8b_custom;
architecture adder8b_custom of adder8b_custom is
component adder4b
port ( X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_vector (3 downto 0);
C0: in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
C4: out STD_LOGIC);
end component;
signal s1:std_logic_vector ( 7 downto 0); --for addition
signal s2:std_logic_vector ( 7 downto 0); --for subtraction
signal s3, s4, s5, s6: std_logic_vector (3 downto 0);--placeholders
signal i, j, k, l: std_logic;
begin
u1: adder4b port map (X => X (3 downto 0), Y => "0001",c0=>'0', S => s3 (3 downto 0), c4=>i);
s1(3 downto 0) <=s3(3 downto 0) when s3 (3 downto 0) /="1010"
else "0000";
s<=s1;
--u2: adder4b port map (X => X (7 downto 4), Y => "0001" ,c0 => i, S => s4 (3 downto 0), c4=>j);
--s1( 7 downto 4) <= s4( 3 downto 0) when s4( 3 downto 0) /= "1010"
--else "0000";
--s(7 downto 4)<= s1;
end;
As you can see, everything after the signals is messed up and i do know know how to fix it.
I appreciate all input.
If your 4bit adder is working correctly you just need to map carry out from the low nibble to the carry in of the high nibble. Then map your 8bit respectively.
It's been too long since I played with VHDL so I can remember the code you need.
i am implementing 32 bit ALU in VHDL. i found an error. i can't understand why i am getting this..
which is
Cannot update 'in' object out_alu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----==== Entity of AlU with input and Output
entity AlU is Port (
A : in STD_LOGIC_VECTOR (31 downto 0); ---== A input Vector with 32 Bit
B : in STD_LOGIC_VECTOR (31 downto 0); ---== B input Vector with 32 Bit
S : in STD_LOGIC_VECTOR (2 downto 0) ; ---== S select Input Vector 3 bit for operation
out_AlU : in STD_LOGIC_VECTOR (31 downto 0));---== Output of AlU 32
end AlU;
architecture Behavioral of AlU is
begin
Select_for_operation: Process (S) ---= Deffierent Process for AlU with the selection of S
begin
Case S is
when "000" =>
out_AlU <=A xor B ;
when "001"=>
out_AlU <=A Xnor B ;
when "100"=>
out_AlU <=A or B ;
when "101"=>
out_AlU <=A nor B ;
when "110"=>
out_AlU <=A and B ;
when others =>
NULL ;
end case ;
end Process ;
end Behavioral;
Your signal out_ALU is declared as an input to your entity. That's why you can't assign a signal to it (it is read only so to say).
Change it to out and it will likely compile:
entity AlU is Port (
A : in STD_LOGIC_VECTOR (31 downto 0); ---== A input Vector with 32 Bit
B : in STD_LOGIC_VECTOR (31 downto 0); ---== B input Vector with 32 Bit
S : in STD_LOGIC_VECTOR (2 downto 0) ; ---== S select Input Vector 3 bit for operation
out_AlU : out STD_LOGIC_VECTOR (31 downto 0));---== Output of AlU 32
end AlU;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Lab3_Adder1 is
Port ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end Lab3_Adder1;
architecture Behavioral of Lab3_Adder1 is
SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);
begin
c(0) <= cin;
s <= a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
cout <= c(4);
end Behavioral;
Hello, it's the first time im using this forum. I'm doing a wallace tree multiplication on VHDL. The code above is the code for a full adder. I would like to know how do we call a function/component in a main code ? (like in C programing). I would to call this full adder in my main code.
(Sorry for my english if there is any mistake, im french)
You call functions in VHDL just as you do in C - either to initialise constants, signals or variables, or as sequential statements within a process. But that's not important just now.
But you don't call components! That would be like calling an object in C++ - it makes absolutely no sense!
In VHDL you can instantiate components or (simpler!) just entities, and use signals to interconnect their ports. This is (very very crudely) more like declaring objects and sending messages in an object oriented language. This is called "structural VHDL" and often appears at the top level of a VHDL design, to create and interconnect components like CPU, memory interface, FFT processor etc.
Given your entity
entity Lab3_Adder1 is
Port ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end Lab3_Adder1;
I could build an 8-bit adder for example as follows:
entity Adder_8bit is
Port ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
s : out STD_LOGIC_VECTOR (7 downto 0);
cout : out STD_LOGIC);
end Adder_8bit;
architecture Structural of Adder_8bit is
signal carry_int : std_logic; -- between lower and upper halves
begin
-- We need to create and connect up two adders
LSB_adder : entity work.Lab3_Adder1
Port Map(
cin => cin,
a => a(3 downto 0),
b => b(3 downto 0),
s => s(3 downto 0),
cout => carry_int
);
MSB_adder : entity work.Lab3_Adder1
Port Map(
cin => carry_int,
a => a(7 downto 4),
b => b(7 downto 4),
s => s(7 downto 4),
cout => cout
);
end Structural;
You can define VHDL-Functions which replace combinational circuits and which can be called anywhere in the main VHDL-Code similar to C functions.
You need to define a package first where the function definitions go.
======= myAdders.vhdl ==============
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
package myAdders is
function Lab3_Adder1( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0)) return std_logic;
end Lab3_Adder1;
end myAdders;
package body myAdders is
function Lab3_Adder1 ( cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0)) return std_logic is
variable c: std_logic_vector(4 downto 0);
begin
c(0) := cin;
s := a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
return c(4);
end Lab3_Adder1;
end myAdders;
======= topLevel.vhdl ==============
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.myAddres.all;
entity TopLevel is
Port (
cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC_VECTOR (3 downto 0)
);
end TopLevel;
architecture Structural of TopLevel is
signal carry : std_logic;
begin
carry <= Lab3_Adder1(cin, a, b, c);
... and so on ...
end Structural;