I have this VHDL coding, my Boolean Expression is F(w,x,y) = wxy + wx'y' + xy + w'x'y' and I need to convert it to a Behavioral Model. My question is if I coded the Behavioral Model correctly and I think it is wrong but I don't know where the error is in my code?
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity My_Act41 is
Port ( W : in STD_LOGIC;
X : in STD_LOGIC;
Y : in STD_LOGIC;
F : out STD_LOGIC);
end My_Act41;
architecture Behavioral of My_Act41 is
process(W,X,Y)
begin
if((W and X and Y) = "1" and (W and not X and not Y) = "1" and (X and Y) = "1" and (not W and not X and not Y) = "1") then
F<= '1';
else
F<= '0';
end if
end process
end Behavioral;
The use of Behavioral Model in simple explanation is by word of Logic gates rather in DataFlow Model if you know it is by symbol.
Note: Correct me if I'm wrong that's how I understand VHDL using Behavioral Model and Dataflow Model coding
Behavioral Model Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity My_Ac41 is
Port ( W : in STD_LOGIC;
X : in STD_LOGIC;
Y : in STD_LOGIC;
F : out STD_LOGIC);
end My_Ac41;
architecture Behavioral of My_Ac41 is
begin
F <= (W and X and Y) or (W and not X and not Y) or (X and Y) or (not W and not X and not Y);
end Behavioral;
Related
please I need some help with my VHDL code. I am trying to design a Full adder circuit with 2 half adders. I’m using Max Plus II for my design. I have tried compiling but I keep getting errors(node instance instantiates undefined entity). Please I would appreciate any help I can get. Also, I'm very new to VHDL. Kind regards.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
component half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal s1, s2 : STD_LOGIC;
signal c1, c2 : STD_LOGIC;
begin
HA1: half_adder port map (a => a, b => b, sum => s1, cout => c1);
HA2: half_adder port map (a => s1, b => cin, sum => s2, cout => c2);
sum <= s2;
cout <= c1 OR c2;
end Behavioral;
I expect to design a full adder using 2 half adders and an OR gate. I would also like to view the Wave simulation.
Though you have a component statement which defines the interface of your half_adder block, you will need an equivalent entity statement (usually found in its own file) to actually define its inner workings.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end half_adder;
architecture dataflow of half_adder is
begin
cout <= a and b;
sum <= a xor b;
end dataflow;
The component statement tells your compiler to look for a module that matches a specific description; the entity statement actually defines the workings of the module itself.
I am new to VHDL and I have an assignment about it. I have to make a register that can save the value of Y based on the value of the last 2 bits of X. But before that, there is a process to determine Y value to be used, based on a bit of "field", and this process is in the "initial" component. The "initial" component can work as expected but the "Regis" component, which has to save the value of Y, didn't work at all. And I don't know what's the problem, why my "Regis" component doesn't work as I expect. Would you help me to figure out the problem?
this is my top level module vhdl :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity part1 is
Port ( X : in INTEGER;
Y : in INTEGER;
field : in STD_LOGIC;
Z : out INTEGER);
end part1;
architecture Behavioral of part1 is
component initial
Port ( X : in INTEGER;
Y : in INTEGER;
FIELD : in STD_LOGIC;
Y1 : out UNSIGNED(7 DOWNTO 0));
end component;
component regis
Port ( y : in INTEGER;
x : in UNSIGNED(7 DOWNTO 0);
yout : out INTEGER);
end component;
signal yi, xr : unsigned(7 downto 0);
signal yr, yo : integer;
begin
beginone : initial port map (X => X, Y => Y, FIELD => field, Y1 => yi);
xr <= to_unsigned (X, xr'length);
yr <= to_integer(unsigned(yi));
regY : regis port map (y => yr, x => xr, yout => yo);
Z <= yo;
end Behavioral;
"initial" component listing :
signal xb, yb : unsigned(7 downto 0);
begin
xb <= to_unsigned(X, xb'length);
yb <= to_unsigned(Y, yb'length);
initial : process(FIELD, xb, by)
variable ys : unsigned(7 downto 0);
begin
if (FIELD = '1') then
ys := yb;
else ys := xb xor yb;
end if;
Y1 <= ys;
end process;
end Behavioral;
"regis" component listing :
begin
process(x(1), x(0))
begin
if (x(1) = '0' and x(0) = '0') then yout <= 0;
elsif (x(1) = '0' and x(0) = '1') then yout <= y;
elsif (x(1) = '1' and x(0) = '0') then yout <= 2*y;
elsif (x(1) = '1' and x(0) = '1') then yout <= 3*y;
else yout <= y;
end if;
end process;
end Behavioral;
and this is the testbench of the top level module :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity part1_tb is
-- Port ( );
end part1_tb;
architecture Behavioral of part1_tb is
component part1
Port ( X : in INTEGER;
Y : in INTEGER;
field : in STD_LOGIC;
Z : out INTEGER);
end component;
signal x, y : integer;
signal field : std_logic;
signal z : integer;
begin
uut : part1 port map (x => X, y => Y, field => field, z => Z);
stim_proc : process
begin
wait for 100 ns;
x <= 1;
wait for 100 ns;
y <= 2;
wait for 100 ns;
field <= '1';
wait;
end process;
end Behavioral;
if the program runs correctly, it will produce an output value of z = 2 according to the input being tested. but when the testbench simulated results z = 0.
Thanks all.
I'm looking to implement the functions y = a and b; y = (a or b) and (c or d).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity task1_tb is
-- Port ( ); end task1_tb;
architecture Behavioral of task1_tb is
--declaring the component component task1
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC); end component;
signal y,a,b: std_logic;
signal counter: unsigned(1 downto 0):="00";
begin
uut: task1 port map(a => a, b => b, y => y );
end Behavioral;
How can I assign a (bit 1) and b (bit 2) so it will test ever possible value and make a 20ns delay between each combination? I've been trying to learn VHDL these past two days for a school project and not even sure if what I have is right.
You're looking to use a wait for <duration> in your stimulus process.
process
begin
for i in 0 to 2**2-1 loop --2**(number of input bits)-1
(a, b) <= to_unsigned(i,2);
wait for 20 ns;
end loop;
wait;
end process;
Credit to user1155120 for refinements.
I tried to simulate a TFF using Xilinx ISE web pack and ModelSim using following block diagram and structural Code was written using VHDL. But I am unable to get the correct waveform. Due to the T-flip flop is sequential circuit, first I gave the output value as 1 or 0 for one output (Q) to start to the process.
T flip flop truth table and block diagram
simulation waveform
code for AND gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
W : in STD_LOGIC;
Z : out STD_LOGIC);
end AND_GATE;
architecture Behavioral of AND_GATE is
begin
Z <= X AND Y AND W;
end Behavioral;
code for NOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NOR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end NOR_GATE;
architecture Behavioral of NOR_GATE is
begin
c <= A NOR B;
end Behavioral;
code for T-FF:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TFF_2 is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : inout STD_LOGIC;
s : inout STD_LOGIC);
end TFF_2;
architecture STRUCTURAL of TFF_2 is
--declare components being used in T -FF
component TFF is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
component NOR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end component;
component AND_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
W : in STD_LOGIC;
Z : out STD_LOGIC);
end component;
--declare signals
signal S1, S2 : STD_LOGIC;
begin
C1 : AND_GATE port map (Q, T, CLK, S1);
C2 : AND_GATE port map (S, T, CLK, S2);
C3 : NOR_GATE port map (S1, S, Q);
C4 : NOR_GATE port map (S2, Q, S);
end STRUCTURAL;
These files synthesized without any errors but in the simulation expected output was not given.
There are a few suggestions I have.
There are non initialised variables. Add := '0'; at the end of the declarations. Simulation might show "X" or unknown. The Synthesised design will work OK, being the hardware will go to one or zero, but simulators need to be directed.
Some of your output variables have feedback into inputs. The design is asynchronous, being that you are not using a clock of some description to time the iterations. Consider using a process and something like if rising_edge(clk)
I'm learning VHDL and I've come to a halt. I'd like to create a simple gate out of smaller gates (a NAND gate here). Here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ANDGATE2 is
port(
x,y : in STD_LOGIC;
z : out STD_LOGIC
);
end ANDGATE2;
architecture ANDGATE2 of ANDGATE2 is
begin
z <= x AND y;
end ANDGATE2;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOTGATE1 is
port(
x : in STD_LOGIC;
z : out STD_LOGIC
);
end NOTGATE1;
architecture NOTGATE1 of NOTGATE1 is
begin
z <= NOT x;
end NOTGATE1;
library ieee;
use ieee.std_logic_1164.all;
entity NANDGATE2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end NANDGATE2;
architecture NANDGATE2 of NANDGATE2 is
signal c, d: std_logic;
component NOTGATE1
port(
n_in : in STD_LOGIC;
n_out : out STD_LOGIC
);
end component;
component ANDGATE2
port(
a_in1, a_in2 : in STD_LOGIC;
a_out : out STD_LOGIC
);
end component;
begin
N0: ANDGATE2
port map(x, y, c);
N1: NOTGATE1
port map(c, d);
z <= d;
end NANDGATE2;
Here's the code from some tutorial I've been using as a template; it compiles with no problems.
library ieee;
use ieee.std_logic_1164.all;
-- definition of a full adder
entity FULLADDER is
port
(
a, b, c: in std_logic;
sum, carry: out std_logic
);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
use ieee.std_logic_1164.all;
entity FOURBITADD is
port
(
a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic
);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
signal c: std_logic_vector (4 downto 0);
component FULLADDER
port
(
a, b, c: in std_logic;
sum, carry: out std_logic
);
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;
My code compiles with no errors, but with two warnings:
# Warning: ELAB1_0026: p2.vhd : (85, 0): There is no default binding for component "andgate2".(Port "a_in1" is not on the entity).
# Warning: ELAB1_0026: p2.vhd : (87, 0): There is no default binding for component "notgate1".(Port "n_in" is not on the entity).
What gives?
You need to use the same port names on your component and entity declarations.
Right now, for example in your NOTGATE1 entity declaration, you have input port x and output port z, but in the NANDGATE2 architecture, you declare the NOTGATE1 component to have ports n_in and n_out.
This won't cause problems during compilation, since compilation looks at a single unit at a time, and won't see the actual entities. In the elaboration phase, your tools will try to match up the entities to components, but this will fail since the ports don't match.
Not 100% sure, but I think the pins in your component declarations need to match up to the ones in your entity blocks:
component NOTGATE1
port(
x : in STD_LOGIC;
z : out STD_LOGIC
);
end component;
component ANDGATE2
port(
x,y : in STD_LOGIC;
z : out STD_LOGIC
);
Always use explicit port bindings in your port maps, like
port map(a_in1 => x,
a_in2 => y,
a_out => c);
It will make your code also more clear. In big projects it is the first rule of thumb.