I am really confused, because it is a simple code and I dont find the error. Syntax is fine, but in Simulation the Values of Dready and acc_value dont change.
This is my module MVM.vhd:
entity MVM is
port (
CLK: IN std_logic;
RST: IN std_logic;
DREADY: OUT std_logic
);
end entity MVM;
architecture base of MVM is
begin
process(CLK)
variable acc_value : signed(15 downto 0);
begin
IF rising_edge(CLK) then
IF RST='1' THEN
acc_value := (OTHERS => '0'); -- reset
DREADY <= '0';
END IF;
END IF;
END process;
end base;
If Reset is high, it should set the values of Dready and acc_value to "0"
My Testbench:
entity tb_MVM is
-- Port ( );
end tb_MVM;
architecture TEST of tb_MVM is
Component MVM
port (
CLK: IN std_logic;
RST: IN std_logic;
DREADY: OUT std_logic
);
End component;
signal CLK: std_logic;
signal RST: std_logic;
signal DREADY: std_logic;
BEGIN
uut: MVM Port Map(
CLK=>CLK,
RST=>RST,
DREADY => DREADY
);
tb: process
BEGIN
wait for 100ns;
CLK <= '1';
RST <= '1';
wait for 100ns;
CLK <= '0';
wait for 100ns;
CLK <= '1';
RST <= '0';
END PROCESS;
end TEST;
In the Simulation, the DREADY and acc_value are undefined ('X')
Assuming you mean the output before 300ns...
In simplified words: rising_edge() checks a transition from '0' to '1', and is not true for transitions from 'X' to '1'.
You might also want to make sure that RST is stable when CLK actually rises, for example:
tb: process
BEGIN
CLK <= '0';
RST <= '1';
wait for 100ns;
CLK <= '1';
wait for 100ns;
CLK <= '0';
RST <= '0';
END PROCESS;
This brings DREADY and acc_value to zero after 100ns.
Related
I have a basic morse code decoder design implemented in VHDL. It is working fine on an FPGA board but does not work in the test bench.
I guess there is something wrong with the buttons, but I am not sure.
I've tried playing with the clock times in the test bench to no avail.
ARCHITECTURE behavior OF ProjTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LabProject
PORT(
char : IN std_logic_vector(4 downto 0);
save : IN std_logic;
start_read : IN std_logic;
clk : IN std_logic;
p_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal char : std_logic_vector(4 downto 0) := (others => '0');
signal save : std_logic := '0';
signal start_read : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal p_out : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 2 ns;
constant wait_time : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LabProject PORT MAP (
char => char,
save => save,
start_read => start_read,
clk => clk,
p_out => p_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for wait_time;
char <= "00001";
wait for wait_time;
save <= '1';
wait for wait_time;
save <= '0';
wait for wait_time;
char <= "00010";
wait for wait_time;
save <= '1';
wait for wait_time;
save <= '0';
wait for wait_time;
char <= "00000";
wait for wait_time;
save <= '1';
wait for wait_time;
save <= '0';
wait for wait_time;
start_read <= '1';
-- wait for wait_time;
-- start_read <= '0';
wait;
end process;
END;
Here is the entire test bench. The start_read and save signals are controlled with push buttons on the FPGA.
The p_out signal should give the Morse code representation of the given letter bit by bit but it never changes in the test bench. There are no problems on the FPGA as I mentioned.
I'm new on StackOverflow and I'm sorry for eventual error.
I'm workin on VHDL and I have a problem with the Post-Place & Route. While behavioral works correctly, Post-Place & Route has problem and the result remain UNDEFINED for the all the time.
entity step1 is
port ( d: in std_logic_vector (0 to 5);
clk : in std_logic;
RESET: in std_logic;
q: out std_logic_vector (0 to 5)
);
end step1;
architecture Behavioral of step1 is
begin
ff: process (clk)
begin
if (clk'event and clk='1') then
if (RESET = '1') then
q <= "000000";
else
q <= d;
end if;
end if;
end process;
end Behavioral;
I place here the code. It should be a flip flop D that I use to make a pipeline architecture. Thanks for your reply, and please excuse me for any mistake.
Here's the test bench:
entity test_step1 is
end test_step1
ARCHITECTURE behavior OF test_step1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT step1
PORT(
input : IN std_logic_vector(0 to 5);
clk : IN std_logic;
RESET : IN std_logic;
output : OUT std_logic_vector(0 to 5)
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(0 to 5) := (others => '0');
signal clk : std_logic := '0';
signal RESET : std_logic := '0';
--Outputs
signal output : std_logic_vector(0 to 5);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: step1 PORT MAP (
input => input,
clk => clk,
RESET => RESET,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 10 ns;
RESET <= '0';
input <= "111111";
wait for clk_period*10;
input <= "101010";
-- insert stimulus here
wait;
end process;
END;
The first warning messages for HDL Compiler 89 and 648 found on the internet are:
WARNING:HDLCompiler:89 - "my_module" remains a black-box since it has no binding entity.
WARNING:Simulator:648 - "Top_LCD_test.vhd" Line 35. Instance top_lcd is unboundCompiling architecture behavior of entity testbench
This means that the compiler has not fount any entity corresponding to the component used in your testbench.
In your case, the port names of your entity and component didn't match !
Try to use the same names in port for the component and entity :
entity test_step1 is
end test_step1;
ARCHITECTURE behavior OF test_step1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT step1
PORT(
d : IN std_logic_vector(0 to 5);
clk : IN std_logic;
RESET : IN std_logic;
q : OUT std_logic_vector(0 to 5)
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(0 to 5) := (others => '0');
signal clk : std_logic := '0';
signal RESET : std_logic := '0';
--Outputs
signal output : std_logic_vector(0 to 5);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: step1 PORT MAP (
d => input,
clk => clk,
RESET => RESET,
q => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 10 ns;
RESET <= '0';
input <= "111111";
wait for clk_period*10;
input <= "101010";
-- insert stimulus here
wait;
end process;
I am currently slightly confused about my simple counter.
It is implemented as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity simple_counter is
port(
DOUT : out std_logic_vector(3 downto 0);
CE : in std_logic;
CLK : in std_logic;
RSTN : in std_logic
);
end simple_counter;
architecture behavioral of simple_counter is
signal temp : unsigned(3 downto 0);
begin
process(CLK)
begin
if RSTN = '0' then
temp <= (others => '0');
elsif(rising_edge(CLK)) then
if CE = '1' then
if std_logic_vector(temp) = (temp'range => '1') then
temp <= (others => '0');
else
temp <= temp + 1;
end if;
end if;
end if;
end process;
DOUT <= std_logic_vector(temp);
end behavioral;
I use the following testbench for simulation:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.tools_pkg.all;
library work;
--! #class tools_tb
--! #brief Test bench for the tools_tb design
entity counter_tb is
generic (
VOID : integer := 0);
port (
void_i : in std_logic);
end entity counter_tb;
--! #brief
--! #details
architecture sim of counter_tb is
-- Clock period definitions
-- Clock, reset and baud rate definitions
constant CLK_FREQ : integer := 100_000_000;
constant clk_period : time := (1.0 / real(CLK_FREQ)) * (1 sec);
signal end_sim : boolean := false;
signal rstn : std_logic;
signal clk : std_logic;
signal s_en : std_logic := '0';
------------------------------------------------------------------------------
-- DUT signals
------------------------------------------------------------------------------
signal s_dout : std_logic_vector(3 downto 0) := (others => '0');
signal s_ce : std_logic := '0';
begin -- architecture
fifo : entity work.simple_counter
port map (
DOUT => s_dout,
CE => s_ce,
RSTN => rstn,
CLK => clk
);
-- Clock process definitions (clock with 50% duty cycle is generated here).
clk_process : process
begin
if end_sim = false then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- startup and wait for some time
rstn <= '0';
wait for clk_period;
rstn <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
s_ce <= '1';
wait;
end process;
end architecture sim;
I am confused why the counter increases instantly when I set CE <= '1
(see the attached simulation).
Since the counter is implemented in a synchrous process, shouldn't it take a single clock cycle until it is increased from '0' to '1'?
Thanks a lot!
You most likely have a race condition between s_ce and clk. If you will generate the s_ce on the rising edge of clk then you should see that counter works correctly.
I don't know this simulator but to check the race you can expand deltas when counter changes 0->1
I am a beginner in VHDL coding and I have some problem with my simple state machine. I just want this machine to change the output value loc_RL when the state changes. When I am simulating, there is no value (like 'U') for loc_RL.
Here is my code:
library ieee;
use ieee.std_logic_1164.all;
entity RL is
port (clk, reset, pon_RL, rtl_RL, ACDS_RL, LADS_RL, REN_RL, LLO_RL, MLA_RL, GTL_RL : in std_logic;
loc_RL : out std_logic);
end RL;
architecture behavioral of RL is
type STATE_TYPE is (LOCS, REMS, LWLS, RWLS);
signal state : STATE_TYPE;
begin
process(clk, reset)
begin
if reset='1' then
state <= LOCS;
elsif (rising_edge(clk)) then
case state is
when LOCS =>
if pon_RL = '1' then
state <= REMS;
else
state <= LOCS;
end if;
when REMS =>
if pon_RL = '1' then
state <= LWLS;
else
state <= REMS;
end if;
when LWLS =>
if pon_RL = '1' then
state <= RWLS;
else
state <= LWLS;
end if;
when RWLS =>
if pon_RL = '1' then
state <= LOCS;
else
state <= RWLS;
end if;
end case;
end if;
end process;
process(state)
begin
case state is
when LOCS =>
loc_RL <= '1';
when REMS =>
loc_RL <= '0';
when LWLS =>
loc_RL <= '1';
when RWLS =>
loc_RL <= '0';
end case;
end process;
end behavioral;
testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RL_tb is
end RL_tb;
architecture testbench of RL_tb is
component RL
port (clk, reset, pon_RL, rtl_RL, ACDS_RL, LADS_RL, REN_RL, LLO_RL, MLA_RL, GTL_RL : in std_logic;
loc_RL : out std_logic);
end component;
--wejscia
signal tclk : std_logic;
signal treset: std_logic;
signal tpon_RL : std_logic;
signal trtl_RL : std_logic;
signal tACDS_RL : std_logic;
signal tLADS_RL : std_logic;
signal tREN_RL : std_logic;
signal tLLO_RL : std_logic;
signal tMLA_RL : std_logic;
signal tGTL_RL : std_logic;
--wyjscia
signal loc_RL : std_logic;
--definicja zegara
constant clk_period : time := 40 ns;
begin
--inicjalizacja UUT
uut: RL port map (
tclk,
treset,
tpon_RL,
trtl_RL,
tACDS_RL,
tLADS_RL,
tREN_RL,
tLLO_RL,
tMLA_RL,
tGTL_RL
);
process
begin
tclk <= '0';
wait for clk_period/2;
tclk <= '1';
wait for clk_period/2;
end process;
process
begin
treset <= '1';
wait for 10 ns;
treset <= '0';
tpon_RL <= '1';
end process;
end;
It is compiling correctly, I can proceed to the simulation. I am using NCLaunch from Cadence. Thanks in advance for help.
Analyzing, elaborating and simulating your design and testbench gives:
And looking at the testbench shows:
architecture testbench of RL_tb is
component RL
port (
clk,
reset,
pon_RL,
rtl_RL,
ACDS_RL,
LADS_RL,
REN_RL,
LLO_RL,
MLA_RL,
GTL_RL: in std_logic;
loc_RL: out std_logic
);
end component;
--wejscia
signal tclk: std_logic;
signal treset: std_logic;
signal tpon_RL: std_logic;
signal trtl_RL: std_logic;
signal tACDS_RL: std_logic;
signal tLADS_RL: std_logic;
signal tREN_RL: std_logic;
signal tLLO_RL: std_logic;
signal tMLA_RL: std_logic;
signal tGTL_RL: std_logic;
--wyjscia
signal loc_RL: std_logic;
--definicja zegara
constant clk_period: time := 40 ns;
begin
--inicjalizacja UUT
uut:
RL
port map (
tclk,
treset,
tpon_RL,
trtl_RL,
tACDS_RL,
tLADS_RL,
tREN_RL,
tLLO_RL,
tMLA_RL,
tGTL_RL
);
process
begin
tclk <= '0';
wait for clk_period/2;
tclk <= '1';
wait for clk_period/2;
end process;
process
begin
treset <= '1';
wait for 10 ns;
treset <= '0';
tpon_RL <= '1';
end process;
end architecture;
No where is there an assignment to or initial value assigned to an input to the device under test other than clk, reset and tpon_RL.
Looking in the RL process we find that actual state branching out of LOCS depends on reset not being '1':
process (clk, reset)
begin
if reset = '1' then
state <= LOCS;
elsif (rising_edge(clk)) then
case state is
when LOCS =>
if pon_RL = '1' then
state <= REMS;
else
state <= LOCS;
end if;
when REMS =>
What's missing in your testbench stimulus is a release of the reset.
In the unlabeled process:
process
begin
treset <= '1';
wait for 10 ns;
treset <= '0';
tpon_RL <= '1';
end process;
You're missing a final wait statement:
process
begin
treset <= '1';
wait for 10 ns;
treset <= '0';
tpon_RL <= '1';
wait; -- added
end process;
Which prevents you from immediately assigning reset to a '1' again. Without suspension a process will loop, it's only suspending at the one wait statement, after setting reset to a '0' it's immediately setting it to a '1' before the process suspends, reset will only have a '1' value. No signal is updated while any process is active, there's only one projected output waveform value for any time, including the current simulation time. The assignment to a '1' overwrites the assignment to a '0'.
Fixing that gives:
And now we see the state machine is active.
I hate to ask yet another question on here but apparently I'm really useless with simulators :(.
Basically, I have a traffic light controller that is made up of a bunch of different states and a few timers running for different lengths of time. When the system enters a state, it activates a timer and there is an if statement that watches the timer output and points the system to the next state when the timer output value is 1.
This all works fine on the board, but when I simulate it the count ticks to '1' but the next state isn't selected. This can be seen, here:
I've tried to boil the code down into the essentials below, but if you need more context (and are feeling far more generous than I deserve) then the full code is here.
Initialisation:
entity trafficlightcontroller is
port
(
clk : in std_logic;
reset : in std_logic;
ambulance : in std_logic;
smr : in std_logic;
sml : in std_logic;
ssr : in std_logic;
rlmr : out std_logic;
almr : out std_logic;
glmr : out std_logic;
rlsr : out std_logic;
alsr : out std_logic;
glsr : out std_logic
);
end entity;
architecture rtl of trafficlightcontroller is
-- Build an enumerated type for the state machine
-- r=red;a=amber;g=green;c=car waiting;m=main road;s=side road
type state_type is (rmgs, rmas, rmrs, amrs, gmrs, gmrcs, ramrs, rmacs, rmrcs, ramrcs, rmras, rmrs2);
-- Signals to hold the states
signal present_state, next_state : state_type;
signal divclk, reset2, reset2b, reset3, reset3b, reset10, reset20, reset20b, count2, count2b, count3, count3b, count10, count20, count20b: std_logic;
component timer is
generic (
trigger_cnt: natural := 20
);
port (
clk: in std_logic;
reset: in std_logic;
count: buffer std_logic
);
end component timer;
component clockdivider
port(clkin : in std_logic;
dividedclk : out std_logic
);
end component clockdivider;
begin
timer2 : timer generic map (trigger_cnt => 2) port map(divclk,reset2,count2);
timer2b : timer generic map (trigger_cnt => 2) port map(divclk,reset2b,count2b);
timer3 : timer generic map (trigger_cnt => 3) port map(divclk,reset3,count3);
timer3b : timer generic map (trigger_cnt => 3) port map(divclk,reset3b,count3b);
timer10 : timer generic map (trigger_cnt => 10) port map(divclk,reset10,count10);
timer20 : timer generic map (trigger_cnt => 20) port map(divclk,reset20,count20);
timer20b : timer generic map (trigger_cnt => 20) port map(divclk,reset20b,count20b);
divider : clockdivider port map(clk, divclk);
The beginning of the states (including the state shown in the simulation):
case present_state is
--Red light main; green side road
when rmgs=>
reset2 <= '0';
reset2b <= '0';
reset3 <= '0';
reset3b <= '0';
reset20 <= '0';
reset20b <= '0';
rlmr <= '1';
almr <= '0';
glmr <= '0';
rlsr <= '0';
alsr <= '0';
glsr <= '1';
reset10 <= '1';
--if count is complete then move to next state
if ( count10='1' ) THEN
next_state <= rmas;
--otherwise, return to current state
else
next_state <= rmgs;
end if;
Clock process:
--Every clock tick, the next state is selected as the present state.
state_clocked: process(clk)
begin
if ( rising_edge( clk ) ) THEN
present_state <= next_state;
end if;
end process state_clocked;
The line I entered into the simulator to initialise the clock:
force clk 0 0ns, 1 10 ns -repeat 20ns
Your next_state process is missing lots of signals in the sensitivity list. This will probably fix it. VHDL-2008 allows you to use the keyword "all" instead of signal names. If your synthesis tool supports this, it might be worth using.
The rest are suggestions:
With a two process statemachine, reset logic is most often captured in the state_clocked process. And hence, look more like this:
state_clocked: process(clk)
begin
if ( rising_edge( clk ) ) THEN
if Reset = '0' then
present_state <= rmrs;
else
present_state <= next_state;
end if ;
end if;
end process state_clocked;
You can shorten your code significantly if you use a default assignment to assign the "off" value to all signal outputs of the next_state process:
next_state_proc : process (present_state, ssr, ambulance, Count10, Count3, ... )
begin
-- default assignments
reset2 <= '0';
reset2b <= '0';
reset3 <= '0';
reset3b <='0';
reset10 <= '0';
reset20 <= '0';
reset20b <= '0';
rlmr <= '1';
almr <= '0';
glmr <= '0';
rlsr <= '1';
alsr <= '0';
glsr <= '0';
next_state <= present_state ; -- optional
-- Statemachine code starts here
-- Only do assignments that are different from the default.
if ssr = '0' then
-- Do you change the values from the defaults here?
-- with the defaults, it is not necessary to do any assignments here, however,
-- without the defaults these outputs would have latches on them.
case present_state is
when gmrs => next_state <= gmrcs;
when rmas => next_state <= rmacs;
...
end case ;
elsif ambulance = '0' then
-- Do you change the values from the defaults here?
-- with the defaults, it is not necessary to do any assignments here, however,
-- without the defaults these outputs would have latches on them.
case present_state is
when gmrs | ramrs | ramrcs => next_state <= amrs;
-- when rmas => ???
when rmgs | rmras => next_state <= rmas;
...
end case ;
else
-- main statemachine
case present_state is
when rmgs=>
-- Only drive outputs that are different from the defaults here.
rlsr <= '0';
glsr <= '1';
reset10 <= '1';
--if count is complete then move to next state
if ( count10='1' ) THEN
next_state <= rmas;
--otherwise, return to current state
else
next_state <= rmgs;
end if;
when rmas=>
. . .
end case ;
The reset for the present_state register isn't strictly needed for simulation, but should be there for synthesis.
state_clocked:
process(reset,clk)
begin
if reset = '0' then
present_state <= rmrs;
elsif rising_edge( clk ) THEN
present_state <= next_state;
end if;
end process;
(Jim beat me to it).
process (present_state, reset, ssr, ambulance, count2, count2b,
count3, count3b, count10, count20, count20b)
Adding the process sensitivity elements (and using reset):
(I added a bit more to it. A lot of your design appears to be working to a good extent.)
And think about using a test bench, it would allow automated testing by generating inputs on ambulance, smr, sml and ssr.
library ieee;
use ieee.std_logic_1164.all;
entity tb_tfc is
end entity;
architecture foo of tb_tfc is
signal clk: std_logic := '0';
signal reset: std_logic;
signal ambulance: std_logic := '1';
signal smr: std_logic := '1';
signal sml: std_logic := '1';
signal ssr: std_logic := '1';
signal rlmr: std_logic;
signal almr: std_logic;
signal glmr: std_logic;
signal rlsr: std_logic;
signal alsr: std_logic;
signal glsr: std_logic;
begin
DUT:
entity work.trafficlightcontroller
port map (
clk,
reset,
ambulance,
smr,
sml,
ssr,
rlmr, -- out
almr, -- out
glmr, -- out
rlsr, -- out
alsr, -- out
glsr -- out
);
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 1280 ns then
wait;
end if;
end process;
STIMULUS:
process
begin
reset <= '0'; --
wait for 20 ns;
reset <= '1';
wait for 1020 ns;
ssr <= '0';
wait;
end process;
end architecture;