Currently, I have two sets of flags in my Makefile. I comment one out if I want my program to be optimized or if I want more debugging information (see below).
FC = gfortran
# I switch between having one of the following two lines commented
# FFLAGS = -Og -Wall -Wextra -fcheck=all -fbacktrace -fbounds-check
FFLAGS = -O3
MOD='Modules/'
SRC = Modules/pyplot_module.f90
SRC += Modules/logs.f90
SRC += program.f90
OBJ = ${SRC:.f90=.o}
%.o: %.f90
$(FC) -c -J${MOD} $< $(FFLAGS) -o $#
program: $(OBJ)
$(FC) -J${MOD} $(FFLAGS) -o $# $(OBJ)
remake: remove program
clean:
rm -f **/*.o **/*.mod
remove: clean
rm -f program
Is there a way to have two different suffix rules and have a specific one used based on which target I call. I desire something like I have show below. I suspect this is an XY problem, but I don't know how else to approach this.
FC = gfortran
# Notice changes here
DEBUGFFLAGS = -Og -Wall -Wextra -fcheck=all -fbacktrace -fbounds-check
FFLAGS = -O3
MOD='Modules/'
SRC = Modules/pyplot_module.f90
SRC += Modules/logs.f90
SRC += program.f90
OBJ = ${SRC:.f90=.o}
%.o: %.f90
$(FC) -c -J${MOD} $< $(FFLAGS) -o $#
%.o: %.f90 # I want this suffix rule to be used only when program-debug target is made
$(FC) -c -J${MOD} $< $(DEBUGFFLAGS) -o $#
program-optimized: $(OBJ)
$(FC) -J${MOD} $(FFLAGS) -o $# $(OBJ)
program-debug: $(OBJ)
# But I also want the SRC files to be compiled with these flags aswell
$(FC) -J${MOD} $(DEBUGFFLAGS) -o $# $(OBJ)
remake: remove program
clean:
rm -f **/*.o **/*.mod
remove: clean
rm -f program
You can use target-specific variables to do this, like this:
DEBUGFFLAGS = -Og -Wall -Wextra -fcheck=all -fbacktrace -fbounds-check
FFLAGS = -O3
EXTRAFLAGS =
%.o: %.f90
$(FC) -c -J${MOD} $< $(FFLAGS) $(EXTRAFLAGS) -o $#
program-optimized program-debug: $(OBJ)
$(FC) -J${MOD} $(FFLAGS) $(EXTRAFLAGS) -o $# $(OBJ)
program-debug: EXTRAFLAGS = $(DEBUGFLAGS) # this is the magic
However, this is a bad idea.
The problem is make won't rebuild your object files when you change the flags, it only rebuilds when the files are edited. So, whenever you run make you could have some mix of object files compiled with optimized options and debug options, and you'll never know which are which unless you completely clean all object files in between builds.
Much better is to create a separate subdirectory to hold the object files built for debug versus optimized, then they don't conflict with each other.
Related
As showed in first screenshot, my ideal AVR project structure is that:
*.o, *.elf and *.hex files are in build folder.
PomoScheler.c and pinDefines.h as main files are in root folder, while other *.c and *.h are in src folder.
But *.o are always generated at the same folder as *.c like showed in second screenshot, no matter how.
(I attached my endeavors and whole Makefile below the screenshots)
Firstly, I tried build/ before $#, in vain. The terminal still the same.
# My first Makefile endeavor
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o build/$#
# Terminal command generated by Makefile (Look at the end: *.o path still same as *.c)
avr-gcc -Os -g -std=gnu99 -Wall -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums -ffunction-sections -fdata-sections -DF_CPU=1000000UL -DBAUD=9600UL -I. -I~/Developer/bin/avr8-gnu-toolchain-darwin_x86_64/avr/include -mmcu=atmega328p -c -o src/RotaryEncoder.o src/RotaryEncoder.c
Secondly, I tried to add mv $# build to explicitly move it to build folder. But nothing happened. Even echo are not displayed in Terminal.
# My second Makefile endeavor
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $#
mv $# build
echo ---------Hello---------
Thirdly, I delete $(HEADERS) and replace $< with $^ just to have a try. The mv is executed. But it cannot find *.o file this time even though I have VPATH = src:build in Makefile.
# My third Makefile endeavor
%.o: %.c
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $^ -o $#
mv $# build
# Terminal error
Assembler messages:
Fatal error: can't create build/src/RotaryEncoder.o: No such file or directory
And my whole Makefile is here. Please help me out.
# My whole Makefile
MCU = atmega328p
F_CPU = 1000000UL
BAUD = 9600UL
LIBDIR = ~/Developer/bin/avr8-gnu-toolchain-darwin_x86_64/avr/include
PROGRAMMER_TYPE = usbtiny
PROGRAMMER_ARGS =
CC = avr-gcc
OBJCOPY = avr-objcopy
OBJDUMP = avr-objdump
AVRSIZE = avr-size
AVRDUDE = avrdude
##########------------------------------------------------------##########
VPATH = ./src:./build
TARGET = $(lastword $(subst /, ,$(CURDIR)))
SOURCES=$(wildcard *.c src/*.c $(LIBDIR)/*.c)
OBJECTS=$(SOURCES:.c=.o)
HEADERS=$(SOURCES:.c=.h)
CPPFLAGS = -DF_CPU=$(F_CPU) -DBAUD=$(BAUD) -I. -I$(LIBDIR)
CFLAGS = -Os -g -std=gnu99 -Wall
CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
CFLAGS += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,-Map,build/$(TARGET).map
LDFLAGS += -Wl,--gc-sections
TARGET_ARCH = -mmcu=$(MCU)
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o build/$#
$(TARGET).elf: $(OBJECTS)
$(CC) $(LDFLAGS) $(TARGET_ARCH) $^ $(LDLIBS) -o build/$#
%.hex: %.elf
$(OBJCOPY) -j .text -j .data -O ihex build/$< build/$#
all: $(TARGET).hex
size: $(TARGET).elf
$(AVRSIZE) -C --mcu=$(MCU) $(TARGET).elf
clean:
rm -f $(TARGET).elf $(TARGET).hex $(TARGET).obj \
$(TARGET).o $(TARGET).d $(TARGET).eep $(TARGET).lst \
$(TARGET).lss $(TARGET).sym $(TARGET).map $(TARGET)~ \
$(TARGET).eeprom
flash: $(TARGET).hex
$(AVRDUDE) -c $(PROGRAMMER_TYPE) -p $(MCU) $(PROGRAMMER_ARGS) -U flash:w:$<
This is clearly not right:
OBJECTS = $(SOURCES:.c=.o)
because the object files you want to create are not foo.o etc. which is what this will expand to; the object files are build/foo.o etc. So this has to be:
OBJECTS = $(patsubst %.c,build/%.o)
All of your attempts to trick make by telling it your recipe will build one target (foo.o) but actually building a totally different target (build/foo.o) are doomed to fail, regardless of whether you have the compiler do it directly, you use mv, or any other method.
If you just tell make what your recipe actually does, you will have a much simpler time of it:
build/%.o: %.c
mkdir -p $(#D)
$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $^ -o $#
Probably you have similar issues with the other rules that you want to put into other directories.
You can't do this by trying to hide it from make. Make has to know where the files actually are.
BTW, VPATH cannot help here. VPATH is for finding source files, it cannot be used for finding generated files. So you could use VPATH to find your .c files but not your .o files.
I am using this auto-generated Makefile with pattern rules, that I oviously do not understand yet. I want to create debuggins symbols and then debug main, but it doesn't work. There is a -g flag. Adding $(LDFLAGS) statement above after $(ODIR) does not print one as expcted.
IDIR =./include
CC=g++
CFLAGS = -I$(IDIR)
LDFLAGS = -g
ODIR=./
LIBS=
_OBJ = main.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
$(ODIR)/%.o: %.c
$(CC) -c -o $# $< $(CFLAGS)
main: $(OBJ)
$(CC) $(LDFLAGS) -o $# $^ $(CFLAGS) $(LIBS)
.PHONY: clean
clean:
rm -f $(ODIR)/*.o
This is the terminal output
g++ -c -o Source.o Source.cpp
g++ -g -o Source Source.o -I./include
Your sources are C++ (.cpp) but your Makefile contains explicit instructions for building C files. Make is therefore falling back to its built in implicit rules.
Also note that by convention those rules use $(CXX) to refer to the C++ compiler, with $(CXXFLAGS) replacing $(CFLAGS), and the -I flag belongs in $(CPPFLAGS):
IDIR =./include
CPPFLAGS = -I$(IDIR)
CXXFLAGS = -g
ODIR=.
LIBS=
_OBJ = main.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
$(ODIR)/%.o: %.cpp
$(CXX) -c -o $# $(CPPFLAGS) $(CXXFLAGS) $<
main: $(OBJ)
$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $# $^ $(LIBS)
.PHONY: clean
clean:
rm -f $(OBJ)
If you were to do away with the ODIR handling and use the conventional variable names you could do without the explicit .o: .cpp rule altogether.
can anyone help me in interpreting the following makefile:
# compiler
FC = gfortran
# compile flags
FCFLAGS = -c -ffixed-line-length-72 -std=gnu -Wline-truncation -Wunused-variable
# link flags
FLFLAGS =
# module files
MODULES = Calculator.f
# object files
OBJS = Calculator.o
OBJS += Main.o Common.o Io.o
# program name
PROGRAM = calFap
all: $(PROGRAM)
$(PROGRAM): $(OBJS)
$(FC) $(FLFLAGS) -o $# $^
%.o: %.f
$(FC) $(FCFLAGS) -o $# $^
mod: $(MODULES)
$(FC) $(FCFLAGS) $# $^
clean:
rm -f *.o *.mod
What does this mean:
# module files
MODULES = Calculator.f
Is this just a kind of placeholder? So MODULES is "linked" to Calculator.f ? The file Calculator.f already exists.
# object files
OBJS = Calculator.o
OBJS += Main.o Common.o Io.o
So here I create a variable and I put in Calculator.o Main.o Common.o Io.o . But in my folder they do not exist up to now?
all: $(PROGRAM)
So the internet tells me, that "all" as a target is used in order to compile the whole program? But as far as I understand, makefiles are there for only compiling those parts of a programm which have changed?
$(PROGRAM): $(OBJS)
$(FC) $(FLFLAGS) -o $# $^
If there is a change in one of the OBJS files then something should be compiled. But I do not get the part with "-o $# $^" . Maybe all objects which have changed?
%.o: %.f
$(FC) $(FCFLAGS) -o $# $^
If there is a change in one of the .f files ...? I don't get this line.
For your help I would be really happy.
Thanks Helmut
I am trying to compile this code with gfortran.
Makefile:
# makefile for BIRRP
FC = gfortran
FCFLAGS = -g -fbounds-check
FLFLAGS = -g -fbacktrace
SRC = birrp.f coherence.f dataft.f diagnostic.f fft.f filter.f math.f rarfilt.f response.f rtpss.f utils.f weight.f zlinpack.f
# "make" builds all
PROGRAM = birrp
all: $(PROGRAM)
$(PROGRAM): $(SRC)
$(FC) $(FCFLAGS) $# $<
%.o: %.f
$(FC) $(FLFLAGS) -o $# $^
clean:
rm -f *.o
It doesn't work
gfortran -g -fbounds-check birrp birrp.f
gfortran: error: birrp: No such file or directory
Makefile:13: recipe for target 'birrp' failed
make: *** [birrp] Error 1
I am using the gfortran compiler. I have copied the Makefile from my other program.
After adding -o:
FC = gfortran
FCFLAGS = -g -c -fbounds-check
FLFLAGS = -g -fbacktrace
SRC = birrp.f coherence.f dataft.f diagnostic.f fft.f filter.f math.f rarfilt.f response.f rtpss.f utils.f weight.f zlinpack.f
# "make" builds all
PROGRAM = birrp
all: $(PROGRAM)
$(PROGRAM): $(SRC)
$(FC) $(FCFLAGS) -o $# $<
%.o: %.f
$(FC) $(FLFLAGS) -o $# $^
clean:
rm -f *.o
Now it just compiles
gfortran -g -c -fbounds-check -o birrp birrp.f
Why?
gfortran interprets birrp as a source-file, but you want it as the outfile.
man gfortran
says the outfile is specified by the -o parameter, so your target becomes this:
$(PROGRAM): $(SRC)
$(FC) $(FCFLAGS) -o $# $<
But this doesn't solve all your problems. According to the GNU Make manual $< specifies the first dependency and not all of them. You always want to have the whole list of dependencies, which would be $^.
So your target becomes this:
$(PROGRAM): $(SRC)
$(FC) $(FCFLAGS) -o $# $^
I am trying to make a makefile, which can make an exe for CppUTest. It can not find the headers, what have I done wrong? First time making a makefile, not 100% sure what I'm doing.
#The compiler to use
CC = g++
LINK = -g -pedantic -Wall -lstdc++ -lpthread -ldl -lm -Wl,-rpath,.
COMPILE = -g -O3 -D_THREAD_SAFE -pedantic -Wall -c -Wno-deprecated
#Name of the EXE file to create.
EXE = ./Tests
SRCS = $(shell ls *.cpp)
OBJS = $(subst .cpp,.o,$(SRCS))
#Extra flags to give to the C compiler.
CFLAGS =
#Libraries to include
LIBS= -lCppUTestExt -lCppUTest -lm
#Extra flags to give to the C++ compiler.
CXXFLAGS = -I/home/mg/DS-5-Workspace/Tests/include
#Extra flags to give to compilers when they are supposed to invoke the linker, ‘ld’,
#such as -L. Libraries (-lfoo) should be added to the LDLIBS variable
#instead.
LDFLAGS = -L/home/mg/DS-5-Workspace/Tests/cpputest/lib
#Extra flags to give to the C preprocessor and programs that use it (the C and
#Fortran compilers).
CPPFLAGS =
.SUFFIXES: .o .cpp
.cpp.o:
$(CC) $(CFLAGS) $(CXXFLAGS) $(LDFLAGS) $(COMPILE) $(LIBS) $<
all: $(OBJS)
$(CC) $(CFLAGS) $(CXXFLAGS) $(LDFLAGS) $(LIBS) $(OBJS) -o $(EXE) $(LINK)
-include depend.mak
depend:
g++ -MM $(SRCS) > depend.mak
#static:
#ar -crvs $(a) $(OBJS)
#shared: $(OBJS)
#$(CC) -shared -Wl,-soname -lc -o $(so) $(OBJS)
clean:
rm -rf $(OBJS) depend.mak $(EXE) $(so) $(a)
I have the following error:
error: CppUTest/CommandLineTestRunner.h: No such file or directory
Well, you're mixing up a lot of things.
Let's clean this up and keep only what is needed :
EXE := Tests
SRC_DIR := .
OBJ_DIR := obj
SRC := $(wildcard $(SRC_DIR)/*.cpp)
OBJ := $(SRC:$(SRC_DIR)/%.cpp=$(OBJ_DIR)/%.o)
CPPFLAGS := -I/home/mg/DS-5-Workspace/Tests/include
CPPFLAGS += -MMD -MP -D_THREAD_SAFE
CXXFLAGS := -W -Wall -Wno-deprecated -pedantic -O3 -g
LDFLAGS := -L/home/mg/DS-5-Workspace/Tests/cpputest/lib
LDFLAGS += -Wl,-rpath,.
LDLIBS := -lCppUTestExt -lCppUTest -lm -lstdc++ -lpthread -ldl
.PHONY: all clean fclean re
all: $(EXE)
clean:
$(RM) -f -r $(OBJ_DIR)
fclean: clean
$(RM) -f $(EXE)
re: fclean all
$(EXE): $(OBJ)
$(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $#
# %.a: $(OBJ)
# $(AR) crvs $# $^
# ranlib $#
# %.so: CXXFLAGS += -fPIC
# %.so: $(OBJ)
# $(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $#
$(OBJ_DIR):
#mkdir -p $#
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp | $(OBJ_DIR)
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -o $# -c $<
-include $(OBJ:.o=.d)
Some explanations :
Avoid the $(shell ...) function, because it'll be executed each time the variable is called if assigned with the = operator instead of := operator.
$(CC) is a built-in variable containing cc or gcc (should be equivalent). Use the built-in $(CXX) to use g++.
-g, -pedantic, -O3, -Wno-deprecated and -Wall are compiler flags, they should be in the CFLAGS (for C) or CXXFLAGS (for C++) built-in variables.
-I <path> and -D_THREAD_SAFE are preprocessor flag, thus should be in the CPPFLAGS built-in variable.
-MMD -MP will auto-generate dependency files (.d extension) for each .o file. You can read more here.
.cpp.o: is a suffix rule, and suffix rules are the old-fashioned way of defining implicit rules for make. You should just rely upon these implicit rules make already know about or make your own the modern way.
You don't need to define .SUFFIXES: by yourself for such widely used targets. The variable SUFFIXES is defined to the default list of suffixes before make reads any makefiles. Make 3.82 defines these suffixes by default :
.SUFFIXES: .out .a .ln .o .c .cc .C .cpp .p .f .F .m .r .y .l .ym .yl .s .S .mod .sym .def .h .info .dvi .tex .texinfo .texi .txinfo .w .ch .web .sh .elc .el
If you have any questions, go on.