Reset from Port to internal components connection - vhdl

Question

I have a Module consisting from another module. e.g.
entity Layer is
port (
CLK: IN std_logic; -- Clock
DIN: IN std_logic;
RST: IN std_logic -- Reset
); -- Data
end Layer;
architecture Behavioral Layer is
component MVM
port (
CLK: IN std_logic; -- Clock
DIN: IN std_logic; -- Data
RST: IN std_logic -- Reset
);
end component;
signal MVM_RST: std_logic;
port MAP( DIN => DIN, CLK => CLK, RST => MVM_RST);
process(CLK) is
begin
if rising_edge(CLK) then
IF RST='1' then
MVM_RST <= '1';
ELSE
MVM_RST <= '0';
END IF;
END IF;
END PROCESS;
end Behavioral;
The logic behind this is I have several other modules connected to reset (not shown in this example) and want them to reset at different time steps but all at the beginning
(i dont know if this is runable, because i wrote it only as a minimin example)
my module 'MVM' is something like
IF RST='1' THEN
MVM_RESULT <= '0';
ELSE
MVM_RESULT <= DIN;
END IF;
The In port of the top module (the layer) is getting new data every clock cycle except for the first one. The first clock cycle is reserved for a high impulse of the reset signal. It starts with clock 0 to get a 0->1 transition
When I am looking at my simulation, the module receives data from the 3th cycle (or?). but so I am loosing 2 cycles instead of 1 cycle
The problem behind this is the part
if rising_edge(CLK) then
IF RST='1' then
MVM_RST <= '1';
ELSE
MVM_RST <= '0';
END IF;
As far as I understand, it means in the first cycle MVM_Res is seted to 1 (which is correct), at the second clock cycle is set to 0, this means for me it can receive data from the 3th cycle (or?)
How to avoid the delay of two cycles. I only want a maximum of 1 cycle delay. I also dont want to directly connect my top module-reset to the component-reset
Here is my testbench (I converted the values to std_logic instead std_logic_vectors to have a minimum example)
entity tb_Layer is
end tb_Layer;
architecture TEST of tb_Layer is
component Layer is
port(
CLK,DIN, RST: IN std_logic;
);
end component;
signal CLK, DIN, RST: std_logic;
BEGIN
uut: Layer PORT MAP(
CLK=> CLK, DIN => DIN, RST=> RST);
tb: process
BEGIN
CLK <= '0';
RST <= '1';
DIN <= '0';
wait for 100ns;
CLK <= '1';
wait for 100ns;
RST <= '0';
CLK <= '0';
DIN <= '1';
wait for 100ns;
CLK <= '1';
wait for 100ns;
CLK <= '0';
DIN <= '0';
wait for 100ns;
CLK <= '1';
wait for 100ns;
END PROCESS;
end TEST;
What the component sees:
The problem is that the first edge it transmits the RST high. SO the component sees after half a cycle too late the Reset high. But because of this the component sees a half cycle the 'u' and so the issue occurs.

Answer 1

You still have the same reason as in your other question, the synchronous reset. In that question, you left the stimulating signals undefined in the first clock cycle, and wondered why the result occurred one clock cycle later than you expected. The suggested change removed the first problem, but not your current issue.
BTW, the shown wave diagram does not match the code of the test bench. Therefore, I respond to the wave diagram, because it seems that this is you problem.
Again, the synchronous nature of the internally generated reset signal delays the reset of the component MVM by one cycle:
At the first rising edge of CLK the signal MVM_RST latches the 'U', as this is the value of RST.
At the second rising edge of CLK the signal MVM_RST latches the '1' of RST and resets MVM_RESULT to all zeroes.
At the third rising edge of CLK the signal MVM_RST latches the '0' of RST and let MVM_RESULT take the value of DIN.
If you had evaluated and simulated the shown test bench, it would go like this:
At the first rising edge of CLK the signal MVM_RST latches the '1' of RST and resets MVM_RESULT to all zeroes.
At the second rising edge of CLK the signal MVM_RST latches the '0' of RST and let MVM_RESULT take the value of DIN.
You might want to learn how to display waves of internal signals with your simulator. Then you can look at MVM_RST to see when it is active.