Brief explanation of some input/outputs of RISC-V Core - caching

Question

I am trying to analyze the code of fetch.v file from (https://github.com/ultraembedded/riscv/tree/master/core/riscv), but the designer has no documentation explaining anything and I am very beginner at the world of Verilog and digital design. What do these mean and do ?
,input fetch_accept_i
,input icache_accept_i
,input icache_valid_i
,input icache_error_i
,input [ 31:0] icache_inst_i
,input icache_page_fault_i
,input fetch_invalidate_i
,input branch_request_i
,input [ 31:0] branch_pc_i
,input [ 1:0] branch_priv_i
// Outputs
,output fetch_valid_o
,output [ 31:0] fetch_instr_o
,output [ 31:0] fetch_pc_o
,output fetch_fault_fetch_o
,output fetch_fault_page_o
,output icache_rd_o
,output icache_flush_o
,output icache_invalidate_o
,output [ 31:0] icache_pc_o
,output [ 1:0] icache_priv_o
,output squash_decode_o
The design is very complex. I wish there is a good resource I could read to understand his design

Answer 1

This is a file that describe the fetch unit of the core.
input means that's a input wire of the unit and output an output one.
The goal of this stage is to fetch instructions from the cache/memory and to send it to the decod unit.
Problem is that every implementation is different but basically :
,input fetch_accept_i : fetch is accepted by fetch stage (signal come from decode)
,input icache_accept_i : instruction cache accept the request from fetch unit
,input icache_valid_i : icache answer is valid
,input icache_error_i : icache answer made an error
,input [ 31:0] icache_inst_i : instruction fetch by the cache
,input icache_page_fault_i : cache did a page fault exception\
,input fetch_invalidate_i : fetch was invalid
,input branch_request_i : fetch unit made a branch request
,input [ 31:0] branch_pc_i : branch address of pc
,input [ 1:0] branch_priv_i : current priviledge of the core (M, S or U)
// Outputs
,output fetch_valid_o : fetch request is valid
,output [ 31:0] fetch_instr_o : ?
,output [ 31:0] fetch_pc_o : current pc which is fetch
,output fetch_fault_fetch_o : fetch did a fault
,output fetch_fault_page_o : fault did a page fault
,output icache_rd_o : ?
,output icache_flush_o : flush request to the cache
,output icache_invalidate_o : invalidate request to the cache
,output [ 31:0] icache_pc_o : current pc
,output [ 1:0] icache_priv_o : priviledge mode
,output squash_decode_o : ?
I'm not sure with my answer but according to the name of the signal i can do these assumptions