Makefile: no rule to make target '%.o', needed by '%'. Stop - makefile

Question

I got the following error:
make: *** No rule to make target cardemo.o, needed by cardemo.exe. Stop
Trying to make this makefile
#Makefile for djgpp
#ALLEG =-lalleg
CC =gcc
OBJECTS = cardemo.o
all: cardemo.exe
#executables
cardemo.exe:$(OBJECTS)
$(CC) $(OBJECTS) $(ALLEG) -o $#
clean:
del *.o
del cardemo.exe
This is my first time creating a makefile with the help of Tutorials and Templates from Google just some days ago so excuse me if you find other mistakes thanks.

Answer 1

According to [GNU]: Catalogue of Built-In Rules:
Compiling C programs
n.o is made automatically from n.c with a recipe of the form $(CC) $(CPPFLAGS) $(CFLAGS) -c.
Example:
cardemo.c:
int main()
{
return 0;
}
Makefile:
#Makefile for djgpp
#ALLEG = -lalleg
#CC = gcc
OBJECTS = cardemo.o
all: cardemo.exe
#executables
cardemo.exe: $(OBJECTS)
$(CC) $(OBJECTS) $(ALLEG) -o $#
clean:
del *.o
del cardemo.exe
Output:
(qaic-env) [cfati#cfati-5510-0:/mnt/e/Work/Dev/StackOverflow/q075071635]> ~/sopr.sh
### Set shorter prompt to better fit when pasted in StackOverflow (or other) pages ###
[064bit prompt]> ls
Makefile cardemo.c
[064bit prompt]> make
cc -c -o cardemo.o cardemo.c
cc cardemo.o -o cardemo.exe
[064bit prompt]> ls
Makefile cardemo.c cardemo.exe cardemo.o
Everything went fine, so the only logical conclusion one could draw is that you don't have a file called cardemo.c in the same directory.
If you modify OBJECTS related line (to OBJECTS = cardemo_notexist.o), you will get the same error.
To get past this, either:
Rename the source file from whatever name has now (could it be carddemo.c ?) to cardemo.c
Note: as #Mopower mentioned in a comment, original was Cardemo.c
Rename the object name so it has the source file stem name: OBJECTS = sourcefile_name.o
If renaming any of the 2 items above is not an option (or maybe cardemo.c is located in a different directory), add a compilation rule that will build cardemo.o from sourcefile_name.c:
cardemo.o: sourcefile_name.c
$(CC) $(CPPFLAGS) $(CFLAGS) -c -o $# $<

Answer 2

The problem is that you have putted $(OBJECTS) in the dependencies spot, which means makefile will need to make that file first (if it doesn't exist), so you should add a rule to make objs from c file like this:
%.o: %.c
$(CC) -o $# -c $<
$# means the target name, $< means the first dependency (You can also use $^ here, $^ means all the dependencied).