I need to increase number of inputs in FPGA. Some answers in google tells about ILA but I don't know how to use it. My RTL code has more number of inputs than available switches on FPGA. so, how can I configure myRTL in FPGA?
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1-1 What are the difference in delay times of the basic logic gates?
I found that NAND and NOR gates are preferred in digital circuit design for shorter delay time and that AND and OR gates might even be implemented with NOT and NAND/NOR gates.
1-2 Are there set or known difference in delay time between AND, OR, NOT gates?
For a typical fpga (LUT-based logical elements) there's no difference at all.
Single cell can implement a complex function based on its resulting truth table, and multiple expressions might be folded into single cell, so you wouldn't even find individual and/or/not "gates".
It might be different for ASIC, I don't know. But in a typical fpga you don't have gates, there are ram-based lookup tables, implementing complex functions of its inputs - 4-6 inputs, not just 2.
You'll find that in a big enough design the routing costs are much higher than delays in a single logical cell.
If you look at how these different gates are constructed you can see some of the reasons for differences. An inverter consists of one pull-up transistor and one pull down transistor. This is the simplest gate and is therefore potentially the fastest. A NAND has two pull-down devices in series and two pull-up transistors in parallel. The NOR is basically the opposite of the NAND. And yes: AND is usually just NAND + inverter.
The on resistance of a path will be higher with two transistors in series (making it slower), and the number of transistors connected to a single node will increase the captive load (making it slower). You can make things faster by using larger transistors (with lower on resistance) but that increases the load of whatever cell is driving it, which slows that cell down.
It is a big optimization problem which you probably shouldn't try to solve yourself. That is what the EDA tools are for.
Like most answers in life, it depends. There are many ways to build each type of logic gate and different types of transistors can be used to make each type of gate. You can build all gates from multiple universal gates like NAND and NOR. So the other gates would have a larger delay time. BJT transistors will have a larger delay than MOFET transistors. You can also use Schottky transistors to reduce delays compared to BJT. If you use an IC there are lots of components within the chip, some which may reduce delays and some that may increase delays. So you really have to compare what you are working with. Here is a video that shows the design of logic gates at the transistor level. https://youtu.be/nB6724G3b3E
As a firmware engineer, how do you compare the computation cost of the following operations (maybe amount of resources needed)
addition/subtraction
multiplication
division
trigonometric functions such as cosine
square root
For FLOATING point with 32 bits calculation.
Answer from a hardware (not firmware) point of view: unfortunately there is no simple answer to your question. Each function you listed has many different hardware implementations, usually between small-slow and large-fast. Moreover it depends on your target FPGA because some of them embed these functions as hard macros, so the question is not any more what do they cost, but do I have enough of them in this FPGA?
As a partial answer you can take this: with the most straightforward, combinatorial implementation, not using any hard macro, an integer or fixed-point N-bits adder/subtracter costs O(N) while a N x N-bits multiplier costs O(NxN). Roughly.
For the other functions, it is extremely difficult to answer, there are far too many variants to consider (fixed/floating point, latency, throughput, accuracy, range...). Assuming you make similar choices for all of them, I would say: add < mul < div < sqrt < trig. But honestly, do not take this for granted. If you are working with floating point numbers, for instance, the adder might be closer or even larger than the multiplier because it requires mantissas alignment, that is a barrel shifter.
A firmware engineer with a little hardware design knowledge would likely use premade cores for each of those functions. Xilinx, Altera, and others provide parametrizeable cores that can perform most of the functions that you specified. The parameters for the core will likely include input size and number of cycles taken for the specified operation, among many others. The resources used by each of these cores will vary significantly based on the configuration and also what vendor and corresponding FPGA family that the core is being created for ( for instance Altera Cyclone 5 or Xilinx Artix 7). The latency that the cores will have will need to be a factor in your decision as well, higher speed families of FPGAs can operate at faster clock rates decreasing the time that operations take.
The way to get real estimates is to install the vendors tools ( for instance Xilinx's Vivado or Altera's Quartus) and use those tools to generate each of the types of cores required. You will need pick an exact FPGA part, in the family that you are evaluating. Choose one with many pins to avoid running out of I/O on the FPGA. Then synthesize and implement a design for every of the cores you are evaluating. The simplest design will have just the core that you are evaluating and map it's inputs and outputs to the FPGAs I/O pins. The implementation results will give you the number of resources that the design takes and also the maximum clock frequency that the design can run at.
I have an small presentation about FPGA techonology. My questions is: If your FPGA has 85k logic cells, does this mean it can run 85k operations simultaneously?
What I am trying to achieve is to shock the audience with some crazy illustrated facts about FPGA technology or facts. The people who listens now very little about FPGA, so I want to impress them.
What's inside a 'cell' can vary per manufacturer, but the Xilinx definition (using this manufacturer as an example, as these are the devices that I'm familiar with) is one four-input look-up table, and one register. Xilinx devices are made up of a number of 'slices', and these contain a number of functional elements. These might include:
Look-up tables
Registers
Multiplexers
Logic for use in carry chains
etc
As an example, a Spartan6 LX4 has 600 slices, and the marketing material claims that this is equivalent to 3840 'logic cells'. You can look in the user guide for a device to determine exactly what is contained inside a slice.
In addition to this, there are other resources such as multipliers, memories, PLLs, etc.
I suppose you could say that one logic cell can perform one operation, but a single cell is only capable of very simple operations, for example an AND gate, 2:1 multiplexer, etc.
I would say no, but it depends on what you mean by an operation. A logic cell has the capability to implement a number of logical functions (and/or/xor), and it has the ability to hold a state with storage elements. These two functions are how every digital system under the sun operates. Even addition and subtraction are higher level constructs built on top of logical functions. As in other answers, FPGA manufacturers publish guides on what is inside of their logic cell. It is this fundamental cell that is stamped repeatedly in the die to create this "array" as in Field Programmable Gate "Array".
This yields a distinctly "more or less" answer. The logic blocks can be used in multiple modes, and you might even be able to pack more than one function in one (including with two independent outputs), but you must also be able to transport meaningful data to work on. It sounds like you have a 7z020 as an example. You may want to note that besides those logic cells, it also has 220 hardware multiply+add blocks. That amount is not random; the surrounding logic is enough to keep them fed in particular cases, every cycle. Looking in 7 Series FPGAs Configurable Logic Block User Guide (UG474), we find that the Logic Cells number given is an estimate of equivalent 4LUT+FF configurations. The reason this number is lower than the number of flipflops (106k) is that the input arguments for the two 5luts you can split a 6lut into must overlap.
i have to build a project that uses an FPGA with the software Modelsim. the project is a range finder or measuring tape.
I already know the basics of modelsim, but I've never done anything like this. the sensor that i am using is an Infra red proximity sensor. https://www.sparkfun.com/products/242 . I am aware that i will need to use an Analog to digital converter, in order for the fpga to recognize the sensor. this sensor also has to rely on is output voltage to determine the distance. the distance will then be displayed on an LCD screen. The problem i have is that i'm not sure where to start.
so if anyone can give any advice, a sample code for this problem or anything it would be appreciated.
Each of these subjects can be a large subject of their own. As it is, you should narrow down your question into something more specific -- where are you stuck? That said, here are some thoughts to help you narrow your questions.
You have correctly identified what you need to do: utilize an A/D converter, and display range (distance) on an LCD screen.
Let's break what you need to do in a little more details.
You need to interface with the A/D converter. For example, what pins are the data pins attached to on your FPGA? How do you need to clock the A/D? Basically, you need to figure out how to get digital samples into your FPGA logic.
You need to convert your digital samples from a voltage to a range. A lookup table is an excellent way to do this. The input to the lookup table will be (digital) voltage, the output will be range.
You need to learn how to interface with an LCD screen/panel. At minimum, you are going to have to learn how to draw/redraw a few characters on the screen representing the range.
Once you have these 3 components, you need to tie them together. The A/D interface in the FPGA will periodically generate voltage values, the lookup table will convert voltages to range, and then you will display the range value on your LCD.
I'm trying to create two precise frequencies at the 100 MHz range which are just a few kHz apart. A PLL isn't is a solution since it can't multiply by such big values.
The only solution I came up with is XOR two frequencies to add them. However this creates other unwanted frequencies which can only be filtered with external components.
How can I do it?
The only method I can think of are to apply the techniques that are used to build "Time To Digital Converters", i.e., FPGA Based High Resolution Time to Digital Converter. This would allow you to create FPGA based oscillators at nearly any speed, at the cost of hardware resources.
If you plan to use this in a production environment, however, you have to deal with the influence of temperature and vdd on the resulting frequencies. I know that there are FPGA based, temperature compensated circuits for just this purpose, but I guess you'll have to dig rather deep into the matter.