I am trying to write a bare metal application on an ARMv8 board. When I signal a SGI, the exception type of the SGI is synchronous while I am expecting it to be either FIQ or IRQ. Can I config it to be an IRQ? Or could someone explain to me why it is synchronous?
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I am learning VFIO in Linux, and found there is a kernel module irq_bypass, which is being used by VFIO. I read its codes, and found it has functions to add/delete irq producer and consumer. The code submitter described as follows,
The IRQ bypass manager here is meant to provide the shim to connect
interrupt producers, generally the host physical device driver, with
interrupt consumers, generally the hypervisor, in order to configure
these bypass mechanism
So I wrote a module to call the irq_bypass interfaces to figure out its working flow.
The kernel module register irq producer and consumer for an interrupt generated by calling 'int' instruction within this module. But I am not sure if I am doing right, since I did NOT see the consumer is being triggered.
Maybe I am wrong in understanding the mechanism of the irq_bypass module, if so, how does it work in virtualization system or why it is needed in KVM/VFIO in Linux?
What would be the bare minimum CSR requirements for a RV32I capable of running machine code generated with GCC?
I'm thinking of a simple fpga-based (embedded) implementation. No virtual memory or linux support is required.
Also, what GCC flags should I use in order to prevent it from using unimplemented CSR related instructions?
I'm still quite confused after scanning through the RISCV Privileged ISA Specification.
Thanks!
Have a look at the RARS simulator as an example of a simple RISC V implementation. It implements sufficient CSRs (e.g. the exception cause, processor status, exception pc, vector table address, etc..) that you can program an interrupt handler.
You'll need:
utvec — sets the exception handler address
ustatus — to enable/disable interrupts,
uscratch — needed by software exception handler,
ucause — tells the reason for exception
uepc — tells the address of uncompleted instruction at exception
And some others. In RARS, you can see the registers implemented in the register display, Control and Status tab.
I believe RARS supports the timer, so has some
CSRs for that. It also provides a floating point unit, so some CSRs
for exceptions for that as well as rounding configuration. For
handling memory access exceptions, it has utval. And then it
offers some counters. See also table 2.2 in Document Version
20190608-Priv-MSU-Ratified
I would think that your usage of CSRs would be restricted to standalone application configuration, e.g. initial bootup, and interrupt handling, both of which would be written in assembly.
Hard to imagine that compiled C code (object files, .o's) would touch the CSRs in any way. If you have an example of that, please share it.
In some environments, the C implementation allows for standalone (e.g. unhosted) programs. It is possible that such a program created by some compiler includes startup configuration and an exception handler though more likely that these would be user supplied. See, for example, http://cs107e.github.io/guides/gcc/
For the ARMv7 architecture, can a FIQ exception pre-empt a currently executing IRQ handler (in IRQ context of course)
Thanks
Yes (that is arguably its primary purpose), unless the IRQ handler has for some crazy reason manually masked FIQs.
IRQs are automatically masked by the core when taking an FIQ exception, but FIQs are not automatically masked by the core when taking an IRQ.
Some, but not all, ARMv6+ processors also support disabling the ability to manually mask FIQs.
I am trying to understand Asynchronous Interrupt handling in kernel, ofcourse through the legendary Understanding the Linux Kernel.
In this process how and who will trigger Kernel Interrupt Handler?
I would like some one to help me correcting this and to clarify my question on
1)How and Who trigger Kernel Interrupt Handler?
2)How to define new or change existing hardware interrupt handlers?
Thank you in Advance!
This picture from Robert Love's "Linux Kernel Development" pretty well describes path of interrupt. Processor interrupts the kernel in the predefined enty point do_IRQ(). If there is corresponding interrupt handler, it will get executed.
To handle interrupt, you should register your interrupt handler with request_irq().
I have a Windows XP application that is using a driver called TVicHW32 which allows me to create an interrupt handler for OS interrupts. Currently I am using a custom ISA card in an industrial chassis with IRQ 5
The interrupt handler code is working and I can see a variable being incremented so the code that sets up and handles the interrupt is working.
The issue I have is that an IO access call fails to generate any IO activity on the ISA bus. I have an address at 0x308 that is used to trigger a start pulse on the ISA bus interface board.
If I trigger this pulse from the main code, for example, from a timer, the pulse is detected on the ISA bus and the card responds.
If I call the exact same function call to access that IO address from within the interrupt handler, nothing appears on the ISA bus. A logic analyser confirms this.
I have emailed the supplier of the driver but that can't help so I was wondering if anyone here has come across this situation and can offer a solution. This is critical to getting this project working and the only solution I can think of is to develop a custom driver with the DDK but as this requires a steep learning curve, I would hope to find an alternative solution.
Thanks
Dave...