I am using Eclipse CDT to develop a C software. I would like to use glib, but it always reports "Unresolved inclusion: ". I have installed glib on my ubuntu:
carl#Carl:~$ dpkg -l | grep libglib
ii libglib-perl 2:1.223-1
ii libglib2.0-0 2.28.6-0ubuntu1
ii libglib2.0-bin 2.28.6-0ubuntu1
ii libglib2.0-cil 2.12.10-1ubuntu1
ii libglib2.0-data 2.28.6-0ubuntu1
ii libglib2.0-dev 2.28.6-0ubuntu1
ii libglib2.0-doc 2.28.6-0ubuntu1
ii libglibmm-2.4-1c2a 2.28.0-1
I am a freshman to C. Although I found some suggestions:
% gcc test.c -Wall -o test `pkg-config --cflags --libs glib-2.0`
But I do not know how to make it work through my Makefile:
CC= gcc
CXX= g++
CFLAGS= -ggdb -g -Wall -O2
CXXFLAGS= $(CFLAGS)
DFLAGS= -DHAVE_PTHREAD #-D_FILE_OFFSET_BITS=64
OBJS= rand.o
PROG= peta
INCLUDES=
LIBS= -lm -lz -lpthread -Lbwt_gen -lbwtgen
SUBDIRS= . bwt_gen
.SUFFIXES:.c .o .cc
.c.o:
$(CC) -c $(CFLAGS) $(DFLAGS) $(INCLUDES) $< -o $#
.cc.o:
$(CXX) -c $(CXXFLAGS) $(DFLAGS) $(INCLUDES) $< -o $#
all:$(PROG)
lib-recur all-recur clean-recur cleanlocal-recur install-recur:
#target=`echo $# | sed s/-recur//`; \
wdir=`pwd`; \
list='$(SUBDIRS)'; for subdir in $$list; do \
cd $$subdir; \
$(MAKE) CC="$(CC)" CXX="$(CXX)" DFLAGS="$(DFLAGS)" CFLAGS="$(CFLAGS)" \
INCLUDES="$(INCLUDES)" $$target || exit 1; \
cd $$wdir; \
done;
lib:
peta:lib-recur $(OBJS) main.o
$(CC) $(CFLAGS) $(DFLAGS) $(OBJS) main.o -o $# $(LIBS)
cleanlocal:
rm -f gmon.out *.o a.out $(PROG) *~ *.a
clean:cleanlocal-recur
Could anybody help me? Thanks.
Append this at the end of your LIBS directive:
$(shell pkg-config --libs glib-2.0)
And this to your CXXFLAGS and CFLAGS:
$(shell pkg-config --cflags glib-2.0)
This will do the job.
Related
Hi I have this makefile:
CC = gcc
AS = nasm
CFLAGS = -ffreestanding -Wall -Wextra -std=c11 -m32 -nostdlib -nostdinc -fno-stack-protector
LDFLAGS = -m elf_i386 -T link.ld
ASFLAGS = -f elf32
SOURCES = $(wildcard src/*.c wildcard src/*.s)
OBJECTS = $(SOURCES:.[s|o]=.o)
INCLUDEPATH = -I inc src/include
OBJDIR = bin/obj
SRCDIR = src/
all: build
build:
ld $(LDFLAGS) $(OBJECTS) -o bin/kernel.bin
iso: build
cp bin/kernel.bin XeonOS/boot
grub-mkrescue -o XeonOS.iso XeonOS/
run: iso
quemu-system-i386 -m 512M -cdrom XeonOS.iso
clean:
rm -rf bin/*.o bin/kernel.bin
%.o: $(SRCDIR)%.c
$(CC) $(INCLUDEPATH) $(CFLAGS) $< -o $(OBJDIR)/$(OBJECTS)
%.o: $(SRCDIR)%.s
$(AS) $(ASFLAGS) $< -o $(OBJDIR)/$(OBJECTS)
And when i execute the command make run i get the following error:
ld -m elf_i386 -T link.ld src/kernel_c.c src/kernel_asm.s -o bin/kernel.bin
ld:src/kernel_c.c: file format not recognized; treating as linker script
Because the kernel_c.c and kernel_asm.s didn' change their extension to .o. How can i change the extension of both .s and .c to .o at the same time?
By the way, I will have another problem, the value of the OBJECTS variable contains the src/ directory but the object files are stored in the bin/obj folder, How can i change that?
When I had this problem last month I just did this:
SOURCES_C := $(wildcard src/*.c)
SOURCES_S := $(wildcard src/*.s)
OBJECTS := $(SOURCES_C:%.c=%.o) \
$(SOURCES_S:%.s=%.o)
I haven't looked at this too deeply but, as far as I know, that's your best bet.
Finally I used the #LightnessRacesinOrbit advice and also used patsubsr so the code is now working:
CC = gcc
AS = nasm
CFLAGS = -m32 -nostdlib -nostdinc -fno-builtin -fno-stack-protector -nostartfiles -nodefaultlibs -Wall -Wextra -Werror
LDFLAGS = -m elf_i386 -T link.ld
ASFLAGS = -f elf32
C_SOURCES = $(wildcard src/*.c)
C_OBJECTS = $(patsubst %.c,%.o, $(notdir $(C_SOURCES) ))
ASM_SOURCES = $(wildcard src/*.s)
ASM_OBJECTS = $(patsubst %.s,%.o, $(notdir $(ASM_SOURCES) ))
INCLUDEPATH = -I src/include
OBJDIR = bin/obj
SRCDIR = src/
.PHONY: build
all: build
build: $(C_OBJECTS) $(ASM_OBJECTS)
ld $(LDFLAGS) $(OBJDIR)/$(ASM_OBJECTS) $(OBJDIR)/$(C_OBJECTS) -o bin/kernel.bin
iso: build
cp bin/kernel.bin XeonOS/boot
grub-mkrescue -o XeonOS.iso XeonOS/
run: iso
bochs -f bochsconfig.cfg -q
clean:
rm -rf XeonOS/boot/kernel.bin
rm -rf bin/obj/*.o bin/kernel.bin
%.o: $(SRCDIR)%.c
$(CC) $(INCLUDEPATH) $(CFLAGS) $< -o $(OBJDIR)/$#
%.o: $(SRCDIR)%.s
$(AS) $(ASFLAGS) $< -o $(OBJDIR)/$#
I compiling my C source files with this code:
CC=clang -std=c11
CFLAGS=-Wall -g
ASSEMBLY=-S -masm=intel
OPTIMIZE=-Ofast
FOLDER_SRC=./src/
FOLDER_BIN=./bin/
FOLDER_ASSEMBLY=./ass/
clean:
rm -f \
$(FOLDER_BIN)1.1-hello $(FOLDER_ASSEMBLY)1.1-hello \
$(FOLDER_BIN)1.2-fahrenheit $(FOLDER_ASSEMBLY)1.2-fahrenheit \
$(FOLDER_BIN)1.2-fahrenheit-floating $(FOLDER_ASSEMBLY)1.2-fahrenheit-floating
all:
$(CC) $(CFLAGS) $(OPTIMIZE) $(FOLDER_SRC)1.1-hello.c -o $(FOLDER_BIN)1.1-hello
$(CC) $(CFLAGS) $(OPTIMIZE) $(FOLDER_SRC)1.2-fahrenheit.c -o $(FOLDER_BIN)1.2-fahrenheit
$(CC) $(CFLAGS) $(OPTIMIZE) $(FOLDER_SRC)1.2-fahrenheit-floating.c -o $(FOLDER_BIN)1.2-fahrenheit-floating
assembly:
$(CC) $(ASSEMBLY) $(OPTIMIZE) $(FOLDER_SRC)1.1-hello.c -o $(FOLDER_ASSEMBLY)1.1-hello
$(CC) $(ASSEMBLY) $(OPTIMIZE) $(FOLDER_SRC)1.2-fahrenheit.c -o $(FOLDER_ASSEMBLY)1.2-fahrenheit
$(CC) $(ASSEMBLY) $(OPTIMIZE) $(FOLDER_SRC)1.2-fahrenheit-floating.c -o $(FOLDER_ASSEMBLY)1.2-fahrenheit-floating
I try to implement some kind of loop to write less. I added this code, but it just generating errors:
FILENAME_SRC := $(wildcard $(FOLDER_SRC)*.c)
FILENAME_BUILD := $(patsubst $(FOLDER_SRC)%.c,%,$(FILENAME_SRC))
echo : $(FILENAME_SRC)
#echo $^
#echo $(FILENAME_BUILD)
build : $(FILENAME_SRC)
$(CC) $(CFLAGS) $(OPTIMIZE) $^ -o $(FILENAME_BUILD)
make echo printing this to the console:
$ make echo
src/1.2-fahrenheit.c src/1.1-hello.c src/1.2-fahrenheit-floating.c
1.2-fahrenheit 1.1-hello 1.2-fahrenheit-floating
make build command generating this error:
$ make build
clang -std=c11 -Wall -g -Ofast src/1.2-fahrenheit.c src/1.1-hello.c src/1.2-fahrenheit-floating.c -o 1.2-fahrenheit 1.1-hello 1.2-fahrenheit-floating
clang.exe: error: no such file or directory: '1.1-hello'
clang.exe: error: no such file or directory: '1.2-fahrenheit-floating'
make: *** [Makefile:21: build] Error 1
I want the expected output to look like when I do make all:
$ make all
clang -std=c11 -Wall -g -Ofast ./src/1.1-hello.c -o ./bin/1.1-hello
clang -std=c11 -Wall -g -Ofast ./src/1.2-fahrenheit.c -o ./bin/1.2-fahrenheit
clang -std=c11 -Wall -g -Ofast ./src/1.2-fahrenheit-floating.c -o ./bin/1.2-fahrenheit-floating
Final solution
CC := clang -std=c11
GCC := gcc -std=c11
CFLAGS := -Wall -g
ASSEMBLY := -Wall -S -masm=intel
OPTIMIZE := -O3 -march=native
SRC := $(wildcard src/*.c)
BIN := $(patsubst src/%.c,bin/%,$(SRC))
ASS := $(patsubst src/%.c,ass/%,$(SRC))
clean:
rm -f bin/* ass/*
build: $(BIN)
$(BIN): bin/%: src/%.c
$(CC) $(CFLAGS) $(OPTIMIZE) $^ -o $#
assembly: $(ASS)
$(ASS): ass/%: src/%.c
$(CC) $(ASSEMBLY) $(OPTIMIZE) $^ -o $#
Really sorry for the clean ass/* though, it cannot be called assembly because the similar folder name in the project.
Your all rule needs to look something like
CC := clang
CFLAGS := -std=c11 -Wall -g -Ofast
targets := bin/1.1-hello bin/1.2-fahrenheit bin/1.2-fahrenheit-floating
.PHONY: all
all: $(targets)
$(targets): bin/%: src/%.c
$(LINK.c) $^ $(LDLIBS) -o $#
I am trying to build my targets with wildcards. Here is my Makefile:
BINARY = main
LDSCRIPT = stm32f4-discovery.ld
PREFIX ?= arm-none-eabi
CC = $(PREFIX)-gcc
LD = $(PREFIX)-gcc
OBJCOPY = $(PREFIX)-objcopy
CFLAGS += -Os -g \
-Wall -Wextra -Wimplicit-function-declaration \
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
-Wundef -Wshadow \
-I$(TOOLCHAIN_DIR)/include \
-fno-common -mcpu=cortex-m4 -mthumb \
-mfloat-abi=hard -mfpu=fpv4-sp-d16 -MD -DSTM32F4
LDSCRIPT ?= $(BINARY).ld
LDFLAGS += --static -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \
-L$(TOOLCHAIN_DIR)/lib/stm32/f4 \
-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
-mthumb -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
OBJS += $(BINARY).o
all: images
images: $(BINARY).images
%.images: %.bin
##printf "*** $* images generated ***\n"
%.bin: %.elf
##printf " OBJCOPY $(*).bin\n"
$(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin
%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32f4.a
##printf " LD $(subst $(shell pwd)/,,$(#))\n"
$(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32f4 $(LDFLAGS)
%.o: %.c Makefile
##printf " CC $(subst $(shell pwd)/,,$(#))\n"
$(Q)$(CC) $(CFLAGS) -o $# -c $<
clean:
$(Q)rm -f *.o
$(Q)rm -f *.d
$(Q)rm -f *.elf
$(Q)rm -f *.bin
-include $(OBJS:.o=.d)
When I make, I get the error:
make: *** No rule to make target `main.bin', needed by `main.images'. Stop.
I am trying to make a single image, so I can change each % to $(BINARY), and this works, but I would like to figure out why this isn't working.
You are likely missing a dependency somewhere down the chain.
Note: Some people forget that the "Makefile" itself, when placed on the dependency line - is also checked for existance. Double check that you haven't renamed it.
Like #MadScientist recommends, "make -d" will be your friend here. Use that to locate the rule/file that should have been found but was not.
I simplified your example (on Linux) and got the same type of error with:
Makefile:
all: main.out
%.out: %.elf
g++ $^ -o $#
%.elf: %.obj
mv $^ $#
%.obj: %.cpp Makefile
g++ -c $^ -o $#
Create main.cpp, see it work, then rename main.cpp to something else that it can't find, run again, see it fail.
Now rename the Makefile itself, see the same failure.
I have a gnu makefile template that has served me well, but when I try to specify a compiler other than the first g++ in my path, it fails.
Here's the template.
CXX = g++
CXXFLAGS = $(INC) $(LIB) -Wall
INC = -I./ -I/usr/local/include
LIB = -L/usr/local/lib
SRCS = \
blah1.cpp
blah2.cpp
OBJS = $(SRCS:.cpp=.o)
DEPS = $(SRCS:.cpp=.d)
PROG = myprog
$(PROG): $(OBJS)
$(CXX) $(CXXFLAGS) -o $# $(OBJS)
%.d: %.cpp
#set -e; rm -f $#; \
$(CXX) -MM $(CXXFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
debug: CXXFLAGS += -O0 -DDEBUG -ggdb
debug: $(PROG)
-include $(DEPS)
.PHONY: clean
clean:
rm -f $(DEPS) $(OBJS) $(PROG)
When I change the compiler from g++ to something like /usr/local/bin/g++46, it still compiles with g++ (/usr/bin/g++ to be exact). Why?
P.S. Any criticisms with the template are welcome. I'm not very comfortable with gnu make; I just crammed and searched the web for a day to come up with this.
You haven't specified your own rule for how to build object files, so Make uses the default implicit rule, which is:
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c
Note $(CXX), not $(CC), which specifies the default C compiler.
I have made a makefile in order to compile my files:
CFLAGS = -O3 -Wall -I /usr/local/cuda/include/
NVCCFLAGS = -O3 -arch sm_20
LDFLAGS = -O3 -L/usr/local/cuda/lib64 -lcudart
EXE = runAPP
app.o:app.cu
$(NVCC) $(NVCCFLAGS) -c $< -o $(CPPFLAGS) $(LIB_PATH) $(LDFLAGS) $#
$(EXE): app.o
$(NVCC) $(NVCCFLAGS) $(CFLAGS) $(LDFLAGS) -o $# $(CPPFLAGS) $(LIB_PATH) app.o \
-lANN_char -lz
cp $# ../bin
But I got this problem:
app.cpp:26:26: error: cuda_runtime.h: No such file or directory
app.cpp:27:18: error: cuda.h: No such file or directory
This is how I include them in the app.cpp:
#include <cuda.h>
#include <cuda_runtime.h>
Why is this problem?
I search something on google, they said that the app.cpp must be always app.cu, is it true?
Thanks in advance.
If your makefile, you have:
CFLAGS = -O3 -Wall -I /usr/local/cuda/include/
NVCCFLAGS = -O3 -arch sm_20
LDFLAGS = -O3 -L/usr/local/cuda/lib64 -lcudart
EXE = runAPP
app.o:app.cu
$(NVCC) $(NVCCFLAGS) -c $< -o $(CPPFLAGS) $(LIB_PATH) $(LDFLAGS) $#
CPPFLAGS should be expanding to nothing; try changing it to CFLAGS, or change CFLAGS to CPPFLAGS.