Object files to different executables - makefile

Question

I have objects files like:
task1.o task2.o task3.o task4.o tasks.o comm.o
I need to link every of task*.o with two of tasks.o comm.o.
manually it looks like:
gcc -Wall -o task1 task1.o tasks.o comm.o
gcc -Wall -o task2 task2.o tasks.o comm.o
So in result i will have 4 executables, task1.exe etc. but when i try to do this with makefile like:
TASKS= task1 task2 task3 task4
TASK_OBJECTS= task1.o task2.o task3.o task4.o
OBJS_SOURCES= tasks.c comm.c
OBJS= tasks.o comm.o
CC=gcc
CFLAGS= -Wall -c -o
all: $(TASKS)
$(TASKS): $(TASK_OBJECTS) $(OBJS)
$(CC) -o $# $(TASK_OBJECTS) $(OBJS)
$(TASK_OBJECTS): %.o: %.c
$(CC) $(CFLAGS) $# $<
$(OBJS): %.o: %.c
$(CC) $(CFLAGS) $# $<
clean:
rm -rf *.o task1 task2 task3 task4
I get:
gcc -Wall -c -o task1.o task1.c
gcc -Wall -c -o task2.o task2.c
gcc -Wall -c -o task3.o task3.c
gcc -Wall -c -o task4.o task4.c
gcc -Wall -c -o tasks.o tasks.c
gcc -Wall -c -o comm.o comm.c
gcc -o task1 task1.o task2.o task3.o task4.o tasks.o comm.o
instead of
gcc -Wall -c -o task1.o task1.c
gcc -Wall -c -o task2.o task2.c
gcc -Wall -c -o task3.o task3.c
gcc -Wall -c -o task4.o task4.c
gcc -Wall -c -o tasks.o tasks.c
gcc -Wall -c -o comm.o comm.c
gcc -o task1 task1.o tasks.o comm.o
gcc -o task2 task2.o tasks.o comm.o
gcc -o task3 task3.o tasks.o comm.o
gcc -o task4 task4.o tasks.o comm.o
What am i doing wrong?

Answer 1

Here:
$(TASKS): $(TASK_OBJECTS) $(OBJS)
$(CC) -o $# $(TASK_OBJECTS) $(OBJS)
You're constructing each executable from all objects. Instead, you should use a static pattern rule (like the one you already use for $(TASK_OBJECTS)):
$(TASKS): % : %.o $(OBJS)
$(CC) -o $# $^
(Note that $^ is the automatic variable for "all prerequisites".)