Is it possible to use makefile variables in prerequisites? My example below is a little backward, but should demonstrate what I'm trying to achieve:
objects_subsystem1 := $(patsubst %.c,%.o,$(wildcard ../src/ss1/*.c))
objects_subsystem2 := $(patsubst %.c,%.o,$(wildcard ../src/ss2/*.c))
all : subsystem1.elf subsystem2.elf
%.elf : $(objects_%)
$(LD) $< -o $#
EDIT:
I'm using GNU Make 3.80 so unfortunately SECONDEXPANSION is not available!
Yes, if you're using GNUMake:
.SECONDEXPANSION:
%.elf : $$(objects_%)
$(LD) $< -o $#
EDIT:
As #bobbogo points out, there is a solution that does not require .SECONDEXPANSION. First, we spell out the rules:
objects_subsystem1 := $(patsubst %.c,%.o,$(wildcard ../src/ss1/*.c))
objects_subsystem2 := $(patsubst %.c,%.o,$(wildcard ../src/ss2/*.c))
objects_subsystem3 := $(patsubst %.c,%.o,$(wildcard ../src/ss3/*.c))
all : subsystem1.elf subsystem2.elf subsystem3.elf
subsystem1.elf : $(objects_subsystem1)
$(LD) $< -o $#
subsystem2.elf : $(objects_subsystem2)
$(LD) $< -o $#
subsystem3.elf : $(objects_subsystem3)
$(LD) $< -o $#
Then we rearrange things a little:
objects_subsystem1 := $(patsubst %.c,%.o,$(wildcard ../src/ss1/*.c))
all : subsystem1.elf
subsystem1.elf : $(objects_subsystem1)
objects_subsystem2 := $(patsubst %.c,%.o,$(wildcard ../src/ss2/*.c))
all : subsystem2.elf
subsystem2.elf : $(objects_subsystem2)
objects_subsystem3 := $(patsubst %.c,%.o,$(wildcard ../src/ss3/*.c))
all : subsystem3.elf
subsystem3.elf : $(objects_subsystem3)
%.elf :
$(LD) $< -o $#
Then we use the eval function:
define RULE_TEMPLATE
objects_subsystem$(1) := $(patsubst %.c,%.o,$(wildcard ../src/ss$(1)/*.c))
all : subsystem$(1).elf
subsystem$(1).elf : $$(objects_subsystem$(1))
endef
$(eval $(call RULE_TEMPLATE,1))
$(eval $(call RULE_TEMPLATE,2))
$(eval $(call RULE_TEMPLATE,3))
%.elf :
$(LD) $< -o $#
Then finish up with a loop (if it's worth it):
define RULE_TEMPLATE
objects_subsystem$(1) := $(patsubst %.c,%.o,$(wildcard ../src/ss$(1)/*.c))
all : subsystem$(1).elf
subsystem$(1).elf : $$(objects_subsystem$(1))
endef
SUBSYSTEMS := 1 2 3 # this can be made automatic...
$(foreach sys,$(SUBSYSTEMS),$(eval $(call RULE_TEMPLATE,$(sys))))
%.elf :
$(LD) $< -o $#
Related
I'm getting the following output from the console when trying to run make.
==== Building Project (debug) ====
process_begin: CreateProcess(NULL, echo Creating obj/Debug, ...) failed.
make (e=2): The system cannot find the file specified.
make[1]: *** [Project.make:90: obj/Debug] Error 2
make: *** [Makefile:30: Project] Error 2
The makefile is generated using premake and I have no experience with makefiles. the make file looks like this:
# Alternative GNU Make workspace makefile autogenerated by Premake
ifndef config
config=debug
endif
ifndef verbose
SILENT = #
endif
ifeq ($(config),debug)
Project_config = debug
else ifeq ($(config),release)
Project_config = release
else
$(error "invalid configuration $(config)")
endif
PROJECTS := Project
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
Project:
ifneq (,$(Project_config))
#echo "==== Building Project ($(Project_config)) ===="
#${MAKE} --no-print-directory -C . -f Project.make config=$(Project_config)
endif
clean:
#${MAKE} --no-print-directory -C . -f Project.make clean
help:
#echo "Usage: make [config=name] [target]"
#echo ""
#echo "CONFIGURATIONS:"
#echo " debug"
#echo " release"
#echo ""
#echo "TARGETS:"
#echo " all (default)"
#echo " clean"
#echo " Project"
#echo ""
#echo "For more information, see https://github.com/premake/premake-core/wiki"
and the premake5.lua file is this:
workspace "Workspace"
configurations { "Debug", "Release" }
project "Project"
kind "ConsoleApp"
language "C++"
targetdir "bin/%{cfg.buildcfg}"
files { "**.h", "**.cpp" }
filter "configurations:Debug"
defines { "DEBUG" }
symbols "On"
filter "configurations:Release"
defines { "NDEBUG" }
optimize "On"
Any ideas on what might be wrong?
Thanks in advance.
Edit: the Project.make file looks like this:
# Alternative GNU Make project makefile autogenerated by Premake
ifndef config
config=debug
endif
ifndef verbose
SILENT = #
endif
.PHONY: clean prebuild
SHELLTYPE := posix
ifeq (.exe,$(findstring .exe,$(ComSpec)))
SHELLTYPE := msdos
endif
# Configurations
# #############################################
RESCOMP = windres
INCLUDES +=
FORCE_INCLUDE +=
ALL_CPPFLAGS += $(CPPFLAGS) -MMD -MP $(DEFINES) $(INCLUDES)
ALL_RESFLAGS += $(RESFLAGS) $(DEFINES) $(INCLUDES)
LIBS +=
LDDEPS +=
LINKCMD = $(CXX) -o "$#" $(OBJECTS) $(RESOURCES) $(ALL_LDFLAGS) $(LIBS)
define PREBUILDCMDS
endef
define PRELINKCMDS
endef
define POSTBUILDCMDS
endef
ifeq ($(config),debug)
TARGETDIR = bin/Debug
TARGET = $(TARGETDIR)/Project.exe
OBJDIR = obj/Debug
DEFINES += -DDEBUG
ALL_CFLAGS += $(CFLAGS) $(ALL_CPPFLAGS) -g
ALL_CXXFLAGS += $(CXXFLAGS) $(ALL_CPPFLAGS) -g
ALL_LDFLAGS += $(LDFLAGS)
else ifeq ($(config),release)
TARGETDIR = bin/Release
TARGET = $(TARGETDIR)/Project.exe
OBJDIR = obj/Release
DEFINES += -DNDEBUG
ALL_CFLAGS += $(CFLAGS) $(ALL_CPPFLAGS) -O2
ALL_CXXFLAGS += $(CXXFLAGS) $(ALL_CPPFLAGS) -O2
ALL_LDFLAGS += $(LDFLAGS) -s
endif
# Per File Configurations
# #############################################
# File sets
# #############################################
GENERATED :=
OBJECTS :=
GENERATED += $(OBJDIR)/main.o
OBJECTS += $(OBJDIR)/main.o
# Rules
# #############################################
all: $(TARGET)
#:
$(TARGET): $(GENERATED) $(OBJECTS) $(LDDEPS) | $(TARGETDIR)
$(PRELINKCMDS)
#echo Linking Project
$(SILENT) $(LINKCMD)
$(POSTBUILDCMDS)
$(TARGETDIR):
#echo Creating $(TARGETDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) mkdir -p $(TARGETDIR)
else
$(SILENT) mkdir $(subst /,\\,$(TARGETDIR))
endif
$(OBJDIR):
#echo Creating $(OBJDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) mkdir -p $(OBJDIR)
else
$(SILENT) mkdir $(subst /,\\,$(OBJDIR))
endif
clean:
#echo Cleaning Project
ifeq (posix,$(SHELLTYPE))
$(SILENT) rm -f $(TARGET)
$(SILENT) rm -rf $(GENERATED)
$(SILENT) rm -rf $(OBJDIR)
else
$(SILENT) if exist $(subst /,\\,$(TARGET)) del $(subst /,\\,$(TARGET))
$(SILENT) if exist $(subst /,\\,$(GENERATED)) rmdir /s /q $(subst /,\\,$(GENERATED))
$(SILENT) if exist $(subst /,\\,$(OBJDIR)) rmdir /s /q $(subst /,\\,$(OBJDIR))
endif
prebuild: | $(OBJDIR)
$(PREBUILDCMDS)
ifneq (,$(PCH))
$(OBJECTS): $(GCH) | $(PCH_PLACEHOLDER)
$(GCH): $(PCH) | prebuild
#echo $(notdir $<)
$(SILENT) $(CXX) -x c++-header $(ALL_CXXFLAGS) -o "$#" -MF "$(#:%.gch=%.d)" -c "$<"
$(PCH_PLACEHOLDER): $(GCH) | $(OBJDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) touch "$#"
else
$(SILENT) echo $null >> "$#"
endif
else
$(OBJECTS): | prebuild
endif
# File Rules
# #############################################
$(OBJDIR)/main.o: main.cpp
#echo $(notdir $<)
$(SILENT) $(CXX) $(ALL_CXXFLAGS) $(FORCE_INCLUDE) -o "$#" -MF "$(#:%.o=%.d)" -c "$<"
-include $(OBJECTS:%.o=%.d)
ifneq (,$(PCH))
-include $(PCH_PLACEHOLDER).d
endif
The error message appears to be associated with this rule from Project.make ...
$(OBJDIR):
#echo Creating $(OBJDIR)
ifeq (posix,$(SHELLTYPE))
$(SILENT) mkdir -p $(OBJDIR)
else
$(SILENT) mkdir $(subst /,\\,$(OBJDIR))
endif
... and I infer from the appearance of CreateProcess in the diagnbostic message that you are trying to perform this build on Windows.
The issue is a failure to create a subdirectory obj/Debug of the working directory. Sometimes such diagnostics are misleading as to the specific nature of the problem, but here are some possibilities:
the Windows branch of the implicated rule appears to be relying on "command extensions" to be enabled in order to create two directories with one mkdir command. They are enabled by default, but they can be disabled either globally or on a per-processes basis. If they are disabled at least for the cmd.exe process in which you are performing your build then the failure you describe is likely. In that case, you could probably work around that particular issue by manually creating the obj directory, but you might face other, similar ones.
Alternatively, you may simply not be authorized to write in the project folder.
I'm working on an advanced makefile that I found in a book. I've got some simple rules inside:
clean to delete binaries
fclean to delete some extra files too (links to binaries generated by ln)
all to make all
re to make fclean then make all
when I do make fclean then make all, it works perfectly. When i do make re, an error occurs:
error: unable to open output file '/Users/malberte/work/libft/bin/libft/common/ft_atoi.o':
'No such file or directory'
1 error generated.
So here is my code:
$(_MODULE_NAME)_OBJS := $(addsuffix $(_OBJEXT),$(addprefix $($(_MODULE_NAME)_OUTPUT)/,$(basename $(SRCS)))) $(DEPS)
$(_MODULE_NAME)_BINARY := $($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(BINARY_EXT)
$(_MODULE_NAME)_EXPOSE_BINARY := $(_ROOT)/$(BINARY)$(BINARY_EXT)
ifneq ($(_NO_RULES),T)
ifneq ($($(_MODULE_NAME)_DEFINED), T)
_CLEAN := clean-$(_MODULE_NAME)
_FCLEAN := fclean-$(_MODULE_NAME)
_ALL := all-$(_MODULE_NAME)
_RE := re-$(_MODULE_NAME)
_IGNORE := $(shell mkdir -p $($(_MODULE_NAME)_OUTPUT))
.PHONY: all re $(_ALL) $(_RE)
re: fclean all
# re: $(_RE)
# $(_RE): $(_FCLEAN) $(_ALL)
all: $(_ALL)
$(_ALL): $($(_MODULE_NAME)_BINARY)
.PHONY: $(_MODULE_NAME)
$(_MODULE_NAME): $($(_MODULE_NAME)_BINARY)
.PHONY: fclean clean $(_CLEAN)
fclean: $(_FCLEAN)
$(_FCLEAN): $(_CLEAN)
rm -rf $($(patsubst fclean-%,%,$#)_EXPOSE_BINARY)
clean: $(_CLEAN)
$(_CLEAN):
rm -rf $($(patsubst clean-%,%,$#)_OUTPUT)
$($(_MODULE_NAME)_OUTPUT)/%.o: $(_MODULE_PATH)/%.c
#$(COMPILE.c) -o '$#' '$<'
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_LIBEXT): $($(_MODULE_NAME)_OBJS)
#if [ "$(LIBMERGE)" = "F" ]; \
then \
$(AR) r '$#' $^; \
ranlib '$#'; \
else \
libtool -static -o '$#' $^; \
fi
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_EXEEXT): $($(_MODULE_NAME)_OBJS)
$(LINK.c) $^ -o '$#'
$(_MODULE_NAME)_DEFINED := T
endif
endif
I've tried lot of things, I really don't understand what is happening when I use make re and it throws the error above.
Someone has an idea please ?
You have this line in your makefile:
_IGNORE := $(shell mkdir -p $($(_MODULE_NAME)_OUTPUT))
which creates the output directory, as the makefile is being parsed. Then you run your clean target which invokes this recipe:
rm -rf $($(patsubst clean-%,%,$#)_OUTPUT)
which causes the output directory to be deleted. Then you run your all target which invokes the compiler and asks it to write the output file to $($(_MODULE_NAME)_OUTPUT)/%.o but that directory no longer exists.
So the compiler gives you the error:
error: unable to open output file '...': No such file or directory
If you run make twice, then the first time you clean and delete the directory, then when you run make all it will run the _IGNORE shell command and create the directory again so it will exist.
If you run make re one time, then the makefile is only parsed one time and the output directory is only created one time (before it's deleted).
Okay thank you so much. It drove me to think about how a makefile really works, so here is my basic solution, thanks to you:
$(_MODULE_NAME)_OBJS := $(addsuffix $(_OBJEXT),$(addprefix $($(_MODULE_NAME)_OUTPUT)/,$(basename $(SRCS)))) $(DEPS)
$(_MODULE_NAME)_BINARY := $($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(BINARY_EXT)
$(_MODULE_NAME)_EXPOSE_BINARY := $(_ROOT)/$(BINARY)$(BINARY_EXT)
ifneq ($(_NO_RULES),T)
ifneq ($($(_MODULE_NAME)_DEFINED), T)
_OUTPUT_TREE := output-tree-$(_MODULE_NAME)
_CLEAN := clean-$(_MODULE_NAME)
_FCLEAN := fclean-$(_MODULE_NAME)
_ALL := all-$(_MODULE_NAME)
_RE := re-$(_MODULE_NAME)
# _IGNORE := $(shell mkdir -p $($(_MODULE_NAME)_OUTPUT))
.PHONY: all re $(_ALL) $(_RE)
re: fclean all
# re: $(_RE)
# $(_RE): $(_FCLEAN) $(_ALL)
all: $(_ALL)
$(_ALL): $($(_MODULE_NAME)_BINARY)
.PHONY: $(_MODULE_NAME)
$(_MODULE_NAME): $($(_MODULE_NAME)_BINARY)
.PHONY: fclean clean $(_CLEAN)
fclean: $(_FCLEAN)
$(_FCLEAN): $(_CLEAN)
rm -rf $($(patsubst fclean-%,%,$#)_EXPOSE_BINARY)
clean: $(_CLEAN)
$(_CLEAN):
rm -rf $($(patsubst clean-%,%,$#)_OUTPUT)
$($(_MODULE_NAME)_OUTPUT)/%.o: $(_MODULE_PATH)/%.c | $(_OUTPUT_TREE)
#$(COMPILE.c) -o '$#' '$<'
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_LIBEXT): $($(_MODULE_NAME)_OBJS)
#if [ "$(LIBMERGE)" = "F" ]; \
then \
$(AR) r '$#' $^; \
ranlib '$#'; \
else \
libtool -static -o '$#' $^; \
fi
$($(_MODULE_NAME)_OUTPUT)/$(BINARY)$(_EXEEXT): $($(_MODULE_NAME)_OBJS)
$(LINK.c) $^ -o '$#'
.PHONY: output-tree $(_OUTPUT_TREE)
output-tree: $(_OUTPUT_TREE)
$(_OUTPUT_TREE):
mkdir -p $($(_MODULE_NAME)_OUTPUT)
$(_MODULE_NAME)_DEFINED := T
endif
endif
I added a prerequisite order to the atomic target
$($(_MODULE_NAME)_OUTPUT)/%.o: $(_MODULE_PATH)/%.c | $(_OUTPUT_TREE)
Here is the rule:
.PHONY: output-tree $(_OUTPUT_TREE)
output-tree: $(_OUTPUT_TREE)
$(_OUTPUT_TREE):
mkdir -p $($(_MODULE_NAME)_OUTPUT)
I'll see if I need more adjustments but it seems to be the right way !
I have a template file, and the configuration script transforms it into the final Makefile. What shoud be the extension of the template?
Example template:
EXEC = $var1
PATH = $var2
CC = $var3
STRIP = $var4
MKDIR = $var5
COPY = $var6
.PHONY: all
all: $(EXEC)
$(EXEC): source.c
$(CC) $< -o $#
$(STRIP) $#
$(MKDIR) $(PATH)
$(COPY) $# $(PATH)/
The variables are replaced by the configuration script.
I am facing a problem of making multiple targets, and want to avoid code duplication in Makefile.
I have many of these:
$(TARGET1): $(OFILES1)
$(LD) $(LDFLAGS) $(OFILES1) -o $(TARGET1)
...
$(TARGET50): $(OFILES50)
$(LD) $(LDFLAGS) $(OFILES50) -o $(TARGET50)
1) How to write it in loop, is it possible?
2) Will it work for defines? :
i=1 ; while [[ $$i -le $(MAX_TARGETS) ]] ; do \
-include $(OFILES$(i):.o=.d); \
((i = i + 1)) ; \
done
Thank you!
Let's start with what you have:
$(TARGET1): $(OFILES1)
$(LD) $(LDFLAGS) $(OFILES1) -o $(TARGET1)
$(TARGET2): $(OFILES2)
$(LD) $(LDFLAGS) $(OFILES2) -o $(TARGET2)
...
$(TARGET50): $(OFILES50)
$(LD) $(LDFLAGS) $(OFILES50) -o $(TARGET50)
Then use some automatic variables to reduce the redundancy:
$(TARGET1): $(OFILES1)
$(LD) $(LDFLAGS) $^ -o $#
$(TARGET2): $(OFILES2)
$(LD) $(LDFLAGS) $^ -o $#
...
$(TARGET50): $(OFILES50)
$(LD) $(LDFLAGS) $^ -o $#
Then rearrange things a little:
$(TARGET1): $(OFILES1)
$(TARGET2): $(OFILES2)
...
$(TARGET50): $(OFILES50)
$(TARGET3) $(TARGET2) ... $(TARGET50):
$(LD) $(LDFLAGS) $^ -o $#
At this point you could write a loop that would be equivalent to the first fifty lines, and another to generate the long list of targets in the final rule, but it's probably a good idea to look first at how you define these variables. Chances are there's a way to reduce all of this into a single pattern rule.
I agree with Beta. Also, somewhere you must be defining all these make variables, anyway: why not just create the prerequisite lists then? However, if you really wanted to do this you can use $(eval ...) like this:
define PREREQ
$(TARGET$I) : $(OFILES$I)
ALLTARGETS += $(TARGET$I)
endef
ALLTARGETS :=
INDEXES := $(shell seq 1 50)
$(foreach I,$(INDEXES),$(eval $(PREREQ)))
$(ALLTARGETS) :
$(LD) $(LDFLAGS) -o $# $^
The eval function can be tricky to understand, so I advise people to avoid it unless they really need it.
How do I change variable value dynamically in makefile?
I want to call specific target depending on value of macro.
For eg.
STATIC_LIB = TRUE
all: makelib $(var)
makelib:
ifeq (${STATIC_LIB}, TRUE)
var=staticlib
else
var=sharedlib
endif
Here i want to call either staticlib target or sharedlib target depending on the value of target.
Code:
.SUFFIXES: .cpp .hpp
# Programs
SHELL = bash
CC = g++
LD = ld
RM = rm
ECHO = /bin/echo
CAT = cat
PRINTF = printf
SED = sed
DOXYGEN = doxygen
STATIC_LIB = TRUE
######################################
# Project Name (generate executable with this name)
TARGET = cs296_exe_28
# Project Paths
PROJECT_ROOT=$(HOME)/Desktop/cs296/cs296_base_code
EXTERNAL_ROOT=$(PROJECT_ROOT)/external
SRCDIR = $(PROJECT_ROOT)/src
OBJDIR = $(PROJECT_ROOT)/myobjs
BINDIR = $(PROJECT_ROOT)/mybins
LIBDIR = $(PROJECT_ROOT)/mylibs
DOCDIR = $(PROJECT_ROOT)/doc
# Library Paths
BOX2D_ROOT=$(EXTERNAL_ROOT)
GLUI_ROOT=/usr
GL_ROOT=/usr
#Libraries
LIBS = -lBox2D -lglui -lglut -lGLU -lGL
# Compiler and Linker flags
CPPFLAGS =-g -O3 -Wall
CPPFLAGS+=-I $(BOX2D_ROOT)/include -I $(GLUI_ROOT)/include
LDFLAGS+=-L $(BOX2D_ROOT)/lib -L $(GLUI_ROOT)/lib
######################################
NO_COLOR=\e[0m
OK_COLOR=\e[1;32m
ERR_COLOR=\e[1;31m
WARN_COLOR=\e[1;33m
MESG_COLOR=\e[1;34m
FILE_COLOR=\e[1;37m
OK_STRING="[OK]"
ERR_STRING="[ERRORS]"
WARN_STRING="[WARNINGS]"
OK_FMT="${OK_COLOR}%30s\n${NO_COLOR}"
ERR_FMT="${ERR_COLOR}%30s\n${NO_COLOR}"
WARN_FMT="${WARN_COLOR}%30s\n${NO_COLOR}"
######################################
SRCS := $(wildcard $(SRCDIR)/*.cpp)
INCS := $(wildcard $(SRCDIR)/*.hpp)
OBJS := $(SRCS:$(SRCDIR)/%.cpp=$(OBJDIR)/%.o)
OBJSNMAIN := $(filter-out $(OBJDIR)/main.o,$(OBJS))
.PHONY: all setup doc clean distclean
ifndef STATIC_LIB
makelib : sharedlib # line 5
else ifeq ( ${STATIC_LIB}, TRUE )
makelib : staticlib # line 7
else
makelib : sharedlib # line 9
endif
all: setup makelib exelib
setup:
#$(ECHO) "Setting up compilation..."
#mkdir -p myobjs
#mkdir -p mybins
#mkdir -p mylibs
$(BINDIR)/$(TARGET): $(OBJS)
#$(PRINTF) "$(MESG_COLOR)Building executable:$(NO_COLOR) $(FILE_COLOR) %16s$(NO_COLOR)" "$(notdir $#)"
#$(CC) -o $# $(LDFLAGS) $(OBJS) $(LIBS) 2> temp.log || touch temp.err
#if test -e temp.err; \
then $(PRINTF) $(ERR_FMT) $(ERR_STRING) && $(CAT) temp.log; \
elif test -s temp.log; \
then $(PRINTF) $(WARN_FMT) $(WARN_STRING) && $(CAT) temp.log; \
else $(PRINTF) $(OK_FMT) $(OK_STRING); \
fi;
#$(RM) -f temp.log temp.err
-include $(OBJS:.o=.d)
$(OBJS): $(OBJDIR)/%.o : $(SRCDIR)/%.cpp
#$(PRINTF) "$(MESG_COLOR)Compiling: $(NO_COLOR) $(FILE_COLOR) %25s$(NO_COLOR)" "$(notdir $<)"
#$(CC) $(CPPFLAGS) -c $< -o $# -MD 2> temp.log || touch temp.err
#if test -e temp.err; \
then $(PRINTF) $(ERR_FMT) $(ERR_STRING) && $(CAT) temp.log; \
elif test -s temp.log; \
then $(PRINTF) $(WARN_FMT) $(WARN_STRING) && $(CAT) temp.log; \
else printf "${OK_COLOR}%30s\n${NO_COLOR}" "[OK]"; \
fi;
#$(RM) -f temp.log temp.err
exe: $(BINDIR)/$(TARGET)
makelib:
ifeq (${STATIC_LIB}, TRUE)
LIB_TYPE = staticlib
else
LIB_TYPE = sharedlib
endif
staticlib:
#$(ECHO) "static"
#ar rcs $(LIBDIR)/libCS296.a $(OBJSNMAIN)
sharedlib:
#$(ECHO) "shared"
#$(CC) -shared -o $(LIBDIR)/libCS296.so $(OBJSNMAIN)
exelib:
$(CC) -L $(LIBDIR) $(LDFLAGS) -o cs296_exelib_28 $(OBJDIR)/main.o -lCS296 $(LIBS)
doc:
#$(ECHO) -n "Generating Doxygen Documentation ... "
#$(RM) -rf doc/html
#$(DOXYGEN) $(DOCDIR)/Doxyfile 2 > /dev/null
#$(ECHO) "Done"
clean:
#$(ECHO) -n "Cleaning up..."
#$(RM) -rf $(OBJDIR) *~ $(DEPS) $(SRCDIR)/*~ $(LIBDIR)
#$(ECHO) "Done"
distclean: clean
#$(RM) -rf $(BINDIR) $(DOCDIR)/html
The solution that you came up with would not work since $(var) would be evaluated before makelib is executed.
What you could do instead is to define makelib conditionally:
STATIC_LIB = TRUE
all : makelib
ifndef STATIC_LIB
makelib : sharedlib # line 5
else ifeq (${STATIC_LIB}, TRUE)
makelib : staticlib # line 7
else
makelib : sharedlib # line 9
endif
An ifndef conditional directive saves from an error that would occur in case STATIC_LIB is not defined.
You can set var value before rule definition:
Edited, Makefile:
STATIC_LIB = TRUE
ifeq (${STATIC_LIB}, TRUE)
var=staticlib
else
var=sharedlib
endif
all: $(var)
staticlib:
echo "staticlib"
sharedlib:
echo "sharedlib"
Test:
make -f Makefile
Output:
echo "staticlib"
staticlib