How should I design makefile hierarchy? - makefile

Question

I'm learning to write make file but I don't really have a clear mind how should I design my makefile hierarchy. It is not easy to describe so I'll post exactly what I have right now and any suggestions are appreciated.
So what I want to ask is
1. Does my common.mk a general practice to contain TOP_DIR variable?
2. How can I make makefile(1) call makefile(2) if l_util objects are missing.
I have such folder hierarchy which I used to learn c++ algorithms:
-learning
- introduction_to_algorithms
- insertion_sort
- insertion_sort.cpp
- makefile(1)
- l_util
- include
- l_util_stlutil.h
- l_util_numberutil.h
- l_util_stlutil.cpp
- l_util_numberutil.cpp
- makefile(2)
- common.mk
where insertion_sort.cpp includes l_util files. Here are my make files:
common.mk:
1 # This must be the first this in Makefile.common
2 TOP_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
3
4 CC := g++
makefile(1):
1 include ../../common.mk
2
3 CPP_SRCS := \
4 insertion_sort.cpp \
5
6 LIBS := \
7
8 OBJS := \
9 insertion_sort.o \
10
11 OTHER_OBJS := \
12 $(TOP_DIR)l_util/l_util_stlutil.o \
13 $(TOP_DIR)l_util/l_util_numberutil.o \
14
15 INCLUDE_PATH := \
16 $(TOP_DIR)l_util/include
17
18 TASK := insertion_sort.tsk
19
20 # Tool invocations
21 $(TASK): $(OBJS) $(OTHER_OBJS)
22 $(CC) -o $(TASK) $(OBJS) $(OTHER_OBJS) $(LIBS)
23 #echo 'Finished building target: $#'
24
25 $(OBJS): $(CPP_SRCS)
26 $(CC) -c -Wall -I$(INCLUDE_PATH) $(CPP_SRCS)
27 #echo 'Finished building target: $#'
28
29 # Other Targets
30 .PHONY: clean
31 clean:
32 -$(RM) $(OBJS) $(OTHER_OBJS) $(TASK)
makefile(2):
1 include ../common.mk
2
3 CPP_SRCS := \
4 l_util_stlutil.cpp \
5 l_util_numberutil.cpp \
6
7 LIBS := \
8
9 OBJS := \
10 l_util_numberutil.o \
11 l_util_stlutil.o \
12
13 $(OBJS): $(CPP_SRCS)
14 $(CC) -c -Wall $(CPP_SRCS)
15 #echo 'Finished building target: $#'
16
17 # Other Targets
18 .PHONY: clean
19 clean:
20 -$(RM) $(OBJS)
When I run make in insertion_sort folder I get:
1 g++ -c -Wall -I../../l_util/include insertion_sort.cpp
2 Finished building target: insertion_sort.o
3 c++ -c -o ../../l_util/l_util_stlutil.o ../../l_util/l_util_stlutil.cpp
4 c++ -c -o ../../l_util/l_util_numberutil.o ../../l_util/l_util_numberutil.cpp
5 g++ -o insertion_sort.tsk insertion_sort.o ../../l_util/l_util_stlutil.o
../../l_util/l_util_numberutil.o
6 Finished building target: insertion_sort.tsk
I don't think line 3 and 4 are generated by makefile(2), it seems like it's been called automatically without calling makefile(2).

Answer 1

add some code in makefile1:
$(OTHER_OBJS):
make -C “The absolute dir of your makefile2"
your should tell makefile1, where is your makefile2, "make -C" will do that, and make makefile1 call makefile2.

Answer 2

You should use GNUmake and take advantage of its include functionality to build a single hierarchy of dependencies across the entire project.
This is, in practice, the only realistic way of creating a make-based build system that does incremental build correctly. This is they way kbuild, the Linux kernel build system works.
See Recursive Make Considered Harmful.