Simple question, is it wrong / not correct usage to have multiple entries of the form:
add_custom_command(TARGET ${Name}
COMMAND DoStuff)
# <some intermediate logic>
add_custom_command(TARGET ${Name}
COMMAND DoYetOtherStuff)
Ok this is pretty clearly bad style, but is it absolutely wrong? What are the repercussions of doing this?
I don't know of any problems in doing this. However, it would be cleaner to just add the two commands into the one add_custom_command call:
add_custom_command(TARGET ${Name}
COMMAND DoStuff
COMMAND DoYetOtherStuff)
Related
I am following the solution in GNU Makefile treating each recipe line as sub-shell command without continuation character
target_compile: PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load
target_compile: copy_shared_object actual_compile_with_sim_opts
#echo PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS} ...
When I make the Makefile, I am able to see the second target_compile fire off but not the first target_compile which has no dependencies and recipe except a variable. I tried adding override before PROJECT_SIM_OPTS and ; at the end of the line but still it is not working.
There is no Error message reported which makes it even harder to detect. In nutshell, I have to embed this piece of code in another Makefile and if the first target would work, I will see a file generated with -LDFLAGS -L${CURRENT_DIR},-lm -load in it. Since this file is being generated without these flags, I am confident to say that first target is not firing.
How can the two target_compile work together?
It turned out to be an ordering issue. In my case
target_compile: copy_shared_object actual_compile_with_sim_opts
#echo PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS} ...
actual_compile_with_sim_opts was running before copy_shared_object
Once I put the dependency like this,
actual_compile_with_sim_opts: copy_shared_object
I was able to get both targets to work with proper flags
Thanks #Beta for all the help.
I am adding quite a few mocks, using cmocka, which require me to alias them using the GC Clinker opetion --wrap=
I am passing a linker option of the format
-Wl,--wrap=foo,--wrap=bar,--wrap=baz,--wrap= ...
Is there any way to shorten it?
-Wl,--wrap=foo,bar,baz,... did not work. Any suggestions?
Is there any way to shorten it?
No.
Why would you want to? If you care about the length of the resulting command line, note that GCC supports response files:
echo "-Wl,--wrap=foo,--wrap=bar,--wrap=baz,--wrap=..." > cmd
gcc #cmd ...
The problem: i want to echo some info when make makefile, the makefile is generated by CMakeLists.txt, and i don't want to echo the info when cmake CMakeLists.txt, what should i do?
In Makefile, the code is like this:
.build-pre:
#echo
#echo "###########################################################"
#echo "######## Welcome to Prosim Build System ###################"
What should i wirte in the CMakeLists.txt so that i can get like these in MakeFile?
You can use add_custom_target function to create a dummy target that has dependencies set to all other targets causing it to be built first.
You can use the ALL option to make it build every time. However, you will still need to use add_dependencies to make it build before every other target.
Finally, use the command-line tool mode of CMake to make it platform independent. (The COMMENT option of add_custom_target may be enough to show the message).
add_custom_target(display_intro ALL COMMAND cmake -E echo Foo)
# ....
add_executable(your_app ...)
add_dependencies(your_app display_intro)
add_library(your_lib ...)
add_dependencies(your_lib display_intro)
For convenience, you could probably wrap the add_executable and add_dependencies in a function or macro.
In a makefile I use there is #-, that is not mentioned in any makefile tutorial I could find.. Could you please explain what #- is for?
For example:
#- $(RM) *.o
The at-sign # tells Make to not print the command line before executing it.
(Manual: Recipe echoing)
The minus sign - tells Make to ignore the result of the command and not fail the target if it was unsuccessful.
(Manual: Errors in recipes)
In your case it's just both of them being used, because somebody did not want to pollute the output with the erase command, and did not want to fail the build if anything goes wrong with the deletion either.
How do I add comments (with echo) in a Makefile so that they're printed when ran?
You should use
target:
#echo "Building!"
Note the #, which tells Make not to display the command itself. Without this the output would look like:
echo "Building!"
Building!
Or, since Make just pushes whatever is in a rule to bash, you could just use a pound to have bash treat it as a comment.
Rule: Dependencies
# Your Comment
Command
Will output
$ make Rule
# Your Comment
Command
all :
echo "Building!"
$(CC) $(OBJECTS) $(LPATH) $(LIBS) -o $(PROGRAM)
Visual C++ nmake has the !message text... preprocessing directive. I have not used GNU make, so I don't if it has it as weel, but quick search shows it has the $(info text...) function.
And inside command blocks you can use echo.
Since a makefile mostly contains commands to be run when building specific targets, I'd say you use just that: echo.