port size does not match connection size - cpu

Question

I have this code:
Alu.v
module ALU(
src1_i,
src2_i,
src3_i,
src4_i,
ctrl_i,
result_o,
zero_o
);
//I/O ports
input [32-1:0] src1_i;
input [32-1:0] src2_i;
input [4-1:0] src3_i;//shmat is 5 bits instruction[10:6]
input [15-1:0] src4_i;//ori have to deal with 'zero-extended' number
input [4-1:0] ctrl_i;
output [32-1:0] result_o;
output zero_o;
//Internal signals
reg [32-1:0] result_o;
wire zero_o;
//Parameter
assign zero_o = (result_o == 0);
//Main function
always #(*) begin
case(ctrl_i)
0 :result_o <= src1_i & src2_i;//and
1 :result_o <= src1_i | src2_i;//or
2 :result_o <= src1_i + src2_i;//add
6 :result_o <= src1_i - src2_i;//substract
7 :result_o <= src1_i < src2_i ? 1 : 0;//set less than
10:result_o <= ~(src1_i - src2_i);//not the result for bne
11:result_o <= (src1_i | {16'b0000000000000000, src4_i});//ori
12:result_o <= ~(src1_i | src2_i);//nor
13:result_o <= src2_i << 16;//lui
14:result_o <= src2_i << src1_i;//sllv
15:result_o <= src2_i << src3_i;//sll
default:result_o <= 0;//default
endcase
end
endmodule
And in the other module:
Simple_Single_CPU.v
.....
ALU ALU(
.src1_i(RSdata_o),
.src2_i(reg_mux_data_o),
.src3_i(instr_o[10:6]),
.src4_i(instr_o[15:0]),
.ctrl_i(ALUCtrl_o),
.result_o(result_o),
.zero_o(zero_o)
);
I have checked that the port size and connection port size is right, but it gives me these warnings:
# ** Warning: (vsim-3015) C:/Users/lypan/Downloads/Lab2/Lab2/code/Simple_Single_CPU.v(116): [PCDPC] - Port size (4 or 4) does not match connection size (5) for port 'src3_i'. The port definition is at: C:/Users/lypan/Downloads/Lab2/Lab2/code/ALU.v(15).
#
# Region: /TestBench/cpu/ALU
# ** Warning: (vsim-3015) C:/Users/lypan/Downloads/Lab2/Lab2/code/Simple_Single_CPU.v(116): [PCDPC] - Port size (15 or 15) does not match connection size (16) for port 'src4_i'. The port definition is at: C:/Users/lypan/Downloads/Lab2/Lab2/code/ALU.v(16).
#
# Region: /TestBench/cpu/ALU
How can I fix the warnings?

Answer 1

The warning is correct.
In module ALU, you have this declaration:
input [4-1:0] src3_i;//shmat is 5 bits instruction[10:6]
This sets the width of src3_i to 4 because 4-1=3, and 3:0 is 4 bits.
But, in Simple_Single_CPU.v, you have:
.src3_i(instr_o[10:6]),
This connects a 5-bit signal (instr_o[10:6]) to a 4-bit port (src3_i).
You must decide whether the signal should really be 4 bits or 5 bits. For example, if you want 5 bits, use:
input [5-1:0] src3_i;//shmat is 5 bits instruction[10:6]