I tried the following make script but it is neither creating any object file not any binary file what is the mistake I have done?
SRC=src
INC=inc
OBJ=obj
BIN=bin
INCS=-I$(INC)
FLAGS=-g -Wall
CC=/usr/sfw/bin/gcc
SRCS=$(wildcard $(SRC)/*.cpp)
OBJS=$(SRCS:$(SRC)/%.cpp=$(OBJ)/%.o)
$(BIN)/out.exe: $(OBJS)
$(CC) $(INCS) $(LIBS) $(FLAGS) $(OBJS) -o $(BIN)/out.exe
$(OBJS) : $(SRCS)
$(CC) $(INCS) $(LIBS) $(FLAGS) -c $<
clean:
rm -f obj/*.o bin/ussd
Below I have given the list of make tools available in my system and their version
/bin - dmake - Sun Distributed Make 7.7
/usr/bin - dmake - Sun Distributed Make 7.7
/usr/ccs/bin - make - Unknow version
/usr/sfw/bin - gmake - GNU Make 3.80
/usr/xpg4/bin - Unknow version
/usr/local/bin - make - GNU Make version 3.79.1
I think you have problem with make targets for the objects files.
I don't have access to a Solaris machine at the moment, but this worked at my Linux machine.
SRC=src
INC=inc
OBJ=obj
BIN=bin
INCS=-I$(INC)
FLAGS=-g -Wall
CC=/usr/sfw/bin/gcc
SRCS=$(wildcard $(SRC)/*.cpp)
OBJS=$(SRCS:$(SRC)/%.cpp=$(OBJ)/%.o)
$(BIN)/out.exe: $(OBJS)
$(CC) $(INCS) $(LIBS) $(FLAGS) $(OBJS) -o $(BIN)/out.exe
$(OBJ)/%.o: $(SRC)/%.cpp
$(CC) $(INCS) $(LIBS) $(FLAGS) -c $< -o $#
clean:
rm -f obj/*.o bin/ussd
Related
I have Makefile. This runs on FreeBSD with gmake and make. In BSD Make command not output log same with gmake.
$ gmake
compile main.cpp
linking myout
$ make
c++ -O2 -pipe -c main.cpp -o main.o
linking myout
$ cat Makefile
TARGET = myout
default: $(TARGET)
SRCS = main.cpp
OBJS = $(SRCS:%.cpp=%.o)
default: $(BIN)
%.o: %.cpp
#echo compile $<
#$(CXX) -c $< -o $#
$(TARGET): $(OBJS)
#echo linking $#
#$(CXX) $(OBJS) -o $#
clean:
#rm -f $(OBJS) $(TARGET)
According to the FreeBSD make documentation, it doesn't support pattern rules. So your rule here:
%.o: %.cpp
#echo compile $<
#$(CXX) -c $< -o $#
in FreeBSD make is just an explicit rule telling make how to build the literal file %.o from the literal file %.cpp. Since you don't try to build a file named %.o (you're trying to build main.o), this rule is ignored / never used.
It looks like if you want something that will work the same way between both versions of make you'll have to restrict yourself to the POSIX standard suffix rules format, like this:
.SUFFIXES: .cpp .o
.cpp.o:
#echo compile $<
#$(CXX) -c $< -o $#
The default build utilities are different. FreeBSD uses a different implementation of make than GNU/Linux. The respective man pages outline differences.
https://forums.freebsd.org/threads/difference-gmake-gnu-and-freebsd-make.28784/
I have a makefile which compiles and links together objects to create an executable. In order to profile, I need to use an additional flag -pg before compiling. Here is my current makefile:
# objects required
OBJS = obj1.o obj2.o
# flags
FC = gfortran
FLAGS = -O3
PROFILEFLAG = -pg
# executable
EXE = program.exe
PROFEXE = program_prof.exe
# suffixes
.SUFFIXES: .o .f90
# rules
%.o: %.f90
$(FC) $(FLAGS) -c $<
default: $(OBJS)
$(FC) $(FLAGS) $(OBJS) -o $(EXE)
profile: $(OBJS)
$(FC) $(FLAGS) $(OBJS) -o $(PROFEXE) $(PROFILEFLAG)
clean:
rm *.o *.mod
Running make profile runs the rule associated with profile, which creates the executable program_prof.exe which can be profiled. However, since the individual dependencies obj1 and obj2 are not compiled with the -pg flag, I cannot profile the code running in those files.
Is there a way I can add a rule such that the individual objects are also recompiled with the -pg flag when I need to profile?
Currently I am editing the individual object dependencies manually to:
%.o: %.f90
$(FC) $(FLAGS) -c $< -pg
which works as expected, but is time consuming (my actual makefile has multiple dependencies in subfolders, all of which need to be edited). Ideally, I am looking for a rule which should recompile individual objects with the `-pg' flag.
You can do exactly what you want, with target-specific variables:
PROFILE :=
%.o : %.f90
$(FC) $(FLAGS) $(PROFILE) -c -o $# $<
default: $(OBJS)
....
profile: PROFILE := -pg
profile: $(OBJS)
....
However, this is not usually the preferred way. Unless you're really diligent about always doing a full clean when switching back and forth between profile and non-profile builds it's very easy to get confused and have some objects compiled with profiling and others compiled without.
As mentioned in the comments, it's better to build them into separate directories:
$(PDIR)/%.o : %.f90
#mkdir -p $(#D)
$(FC) $(FLAGS) -pg -c -o $# $<
$(ODIR)/%.o : %.f90
#mkdir -p $(#D)
$(FC) $(FLAGS) -c -o $# $<
default: $(addprefix $(ODIR)/,$(OBJS))
$(FC) $(FLAGS) $^ -o $#
profile: $(addprefix $(PDIR)/,$(OBJS))
$(FC) $(FLAGS) -pg $^ -o $#
I've just run into the following issue: I've got a Raspi 3B with a GNU toolchain I normally use to build my C++ project on the Raspi itself. As my project has grown quite large, I would now prefer to cross-build it on my Linux PC with crosstool-ng installed. What I need, though, is a makefile, which both works with the toolchain on the Raspi, and the crosstool. This has been my makefile so far:
CC=g++
CFLAGS=-std=c++11 -ggdb -Wall -Wmultichar
LDFLAGS=-L/usr/lib -L/usr/lib/arm-linux-gnueabihf
LIBRARIES=-lpthread -lkeystonecomm -lgps -lpigpio -lGeographic -lmk4 -lcsvparser -lasound -lespeak -lmpg123 -lout123
SRC=main.cpp vfd.cpp relay.cpp keypad.cpp receiver.cpp widgets.cpp tmc.cpp database.cpp sound.cpp
OBJECTS=main.o vfd.o relay.o keypad.o receiver.o widgets.o tmc.o database.o sound.o
EXEC=autoradio
$(EXEC) : $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $(EXEC) $(LDFLAGS) $(LIBRARIES)
$(OBJECTS) : $(SRC)
$(CC) $(CFLAGS) -c $(SRC)
.PHONY: clean
clean:
rm -rf *.o $(EXEC)
The issue is the following: The crosscompiler is called arm-unknown-linux-gnueabi-g++, and the library paths are different. My goal, however, is to start the build process with a simple make command both on my Raspi, and on my host machine. Or will I have to use a configure script?
As I haven't found any useful tutorials on the Web, may anybody please help me. Thx.
OK, after consulting a few sources, I decided to implant a conditional into my makefile, which asks for the CPU environment variable. As Raspbian does not set it, I set the Raspi's architecture as a default. Et voilà, it works:
CPU?=armv7l
ifeq ($(CPU), armv7l)
CC=g++
else
CC=arm-unknown-linux-gnueabi-g++
endif
CFLAGS=-std=c++11 -ggdb -Wall -Wmultichar
ifeq ($(CPU), armv7l)
LDFLAGS=-L/usr/lib -L/usr/lib/arm-linux-gnueabihf
else
LDFLAGS=-L/usr/lib -L/opt/x-tools/arm-unknown-linux-gnueabi/lib
endif
LIBRARIES=-lpthread -lkeystonecomm -lgps -lpigpio -lGeographic -lmk4 -lcsvparser -lasound -lespeak -lmpg123 -lout123
SRC=main.cpp vfd.cpp relay.cpp keypad.cpp receiver.cpp widgets.cpp tmc.cpp database.cpp sound.cpp
OBJECTS=main.o vfd.o relay.o keypad.o receiver.o widgets.o tmc.o database.o sound.o
EXEC=autoradio
$(EXEC) : $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $(EXEC) $(LDFLAGS) $(LIBRARIES)
$(OBJECTS) : $(SRC)
$(CC) $(CFLAGS) -c $(SRC)
.PHONY: clean
clean:
rm -rf *.o $(EXEC)
If I have 3 files, function.h, function.c and my_program.c which calls a method in function.h all in the same directory, what would be the best way to write a makefile so that I end up with a my_program.bc that would actually run when I type in lli my_program.bc? (I need to run a user defined pass that would insert stuff into the functions - should I run the pass on function.bc and test.bc, or should I link before running the pass?)
I've tried llvm-link function.bc my_program.bc with no luck. I feel I'm either missing something simple or going about the whole thing wrong.
Current terrible none-working makefile:
.PHONY: all clean
CC = clang
CFLAGS = -std=gnu99 -D_POSIX_C_SOURCE=200809L -g -Wall
IRFLAGS = -O3 -emit-llvm
TARGET = test
DEPS = functions.h
all: $(TARGET)
bc: test2
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
%.bc: %.c $(DEPS)
$(CC) $(IRFLAGS) -c -o $# $<
test2: test.bc functions.bc
llvm-link -o test2.bc $< functions.bc
test: test.o functions.o
$(CC) $(CFLAGS) -o $# $^
clean:
$(RM) $(TARGET) *.o *.bc
Why not just write a normal Makefile to produce the desired executable,
then use wllvm?
Shameless plug for wllvm:
https://github.com/SRI-CSL/whole-program-llvm
I do not use lli, so I would be interested to hear about how it resolved
any reliance on stdlibc that your program may have.
Whenever I am trying to build something like this in my Makefile -
gcc -o main.o -IStarterWare_Files -c main.c StarterWare_Files/test.h StarterWare_Files/add.h
It throws me error that gcc: cannot specify -o with -c or -S with multiple files. Basically I want my makefile to build the target again if I change for example some macro in one of my header files. My current Makefile is -
EXE = nextgenrsm
CC = gcc
LIBS = StarterWare_Files/
CPPFLAGS = _IStarterWare_Files/
MAIN_OBS = $(patsubst %.c,%.o,$(wildcard *.c))
LIB_OBS = $(patsubst %.c,%.o,$(wildcard StarterWare_Files/*.c))
all: $(EXE)
$(EXE): $(MAIN_OBS) $(LIB_OBS)
$(CC) -o $# $(LDFLAGS) $(MAIN_OBS) $(LIB_OBS) $(LDLIBS)
%.o: %.c
$(CC) -o $# -MD -MP $(CPPFLAGS) $(CFLAGS) -c $^
ALL_DEPS = $(patsubst %.o,%.d,$(MAIN_OBS), $(LIB_OBS))
-include $(ALL_DEPS)
clean:
rm -f $(LIB_OBS) $(EXE) $(MAIN_OBS) $(ALL_DEPS)
.PHONY: all clean
I can't figure out what changes to make to build my executable again if one of the header files is modified. I don't want to do make clean and make again.
The way the automake system handles this is to not use %.o: %.c but instead list the C file and all of the headers in the C file.
So for example:
main.o: main.c StarterWare_Files/test.h StarterWare_Files/add.h
$(CC) -o $# -MD -MP $(CPPFLAGS) $(CFLAGS) -c $^
See makedepends for a tool that will read C files and figure out the make dependencies.