I would like to launch an unit delay RTL simulation using Questasim 10.1. I've looked how to compile the design and I see there is an option +delay_mode_unit for compiling verilog files. My design is vhdl.
Is there an option for this kind of design?
By refering to Modelsim 10.1c User Manual- Chapter 7, Cell Libraries, you can find how Modelsim can support various Verilog ASIC and FPGA cell libraries. Unit Delay Mode is explained one page after in the manual.
Concerning VHDL, I can't find a similar section where Modelsim has a confirmed support. However, in Chapter 14, VHDL VITAL SDF, you can find how to enable timing for VITAL cells only. You can read the following section SDF to VHDL Generic Matching for more help.
Also have a look at Chapter 6, VITAL Usage and Compliance on how to make a working setup for VHDL.
Related
I am currently setting up a Cocotb based verification environment.
I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface).
I get the following message:
Error (suppressible): (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
(I have the Altera Starter version of ModelSim, and indeed FLI is not included).
What surprises me is that the example works with Verilog. From my understanding, Verilog is not using FLI, but VPI.
Can someone explain me a little bit if the need for FLI is mandatory, and what feature can enable it in Cocotb?
Another question: What if my top is in Verilog, but the rest of my design in VHDL? Should it work?
Cocotb has an internal abstraction layer (GPI) for FLI, VPI and VHPI. E.g. if you use Cocotb with GHDL, it's using just VPI. You can try to compile Cocotb against VPI instead of FLI and load the VPI library instead of the FLI library.
I tried Vivado and Quartus, but both of them are quite heavy, and the tools are very complicated for a starter. Is there a lightweight free IDE + Simulator for a starter who is learning VHDL?
VHDL-Simulation:
There are ports of the linux programs GHDL and GTKwave for windows:
https://github.com/ghdl/ghdl/releases
http://gtkwave.sourceforge.net/
http://gtkwave.sourceforge.net/gtkwave.pdf
GHDL is a command line tool to compile VHDL files and "simulate" them. the output is a waveform file, which can be viewed/inspected by gtkwave. You can write some scripts (I would advice PowerShell) to automate the compilation or you can use a build tool.
In my opinion (Quartus) ModelSim / QuestaSim is not lightweight. The Xilinx simulators iSim (included in ISE) and xSim (included in Vivado) are good enough for every day simulations. ghdl is very fast, but does not support all (advanced) VHDL features.
VHDL-IDEs:
If you are familiar with state-of-the art coding environments like Visual Studio, SharDevelop, MonoDevelop, Eclipse or NetBeans then I would say coding HDLs is still in the stone-age !!
All big vendors offer free HDL toolchains, which are paided by the devices, but these tools are only multi-tabbed text editors with a design hierarchy viewer and some buttons to hide the command line tool executions.
The mentioned Sigasi Eclipse plugin (there is also e free version) is new on the market and has some advantages. This plugin is under constant development and still increasing in its features. I tested several versions in the past, but I'm not satisfied with some features so I'm still using ISE :)
As a students I have not the chance to try some professional tools from Aldec, Mentor, ...
For simulation, ModelSim-Altera Starter Edition is a free version of ModelSim provided by Altera, and is very user friendly and widely used. It has a build in editor with VHDL color coding, so you can do editing, compile, and simulation from within ModelSim.
Vivado (Xilinx) and Quartus (Altera) are synthesis tools, which can transform your VHDL design files into a hardware representation that can be downloaded into an FPGA. These synthesis tools are used for step two, after a design has been created and simulated to verify proper operation.
If you are a student, you can get a free student license for Sigasi. It's an eclipse based vhdl IDE, with all the modern IDE features like on the fly error checking, formatting, hovers...
It has integration with Modelsim, ISim and riviera, Sigasi compiles the the vhdl files for you in the background and you can start the simulator with 1 click. It's not the 100% IDE experience but it's as close as you can get for VHDL.
VHDL is complicated and not lightweight. Live with it.
For a list of free simulators, see: http://www.sigasi.com/faq/which-free-vhdl-simulator-can-i-use
I have xilinx macros for uart (.edn files) and i don't know how to use the in activehdl
when i simulate the macros the give uninitialized output ? so what if any one can help me with the right way to use the macro ...?
Use the Xilinx uniMacro library. You may need to compile or download it for your simulator.
ActiveHDL is a simulator package. It typically operates by compile VHDL or Verilog code. The "macros" you are refering to with the extension ".edn" are EDIF netlist files. These are not files that can typically be used by simulator, but are in almost all cases only usable by the synthesizer for the exact device they are targeting.
It may be the case that ActelHDL can import EDIF files. In this case, it still will only work if the primitives used by the EDIF file are also added as part of the project. As another answer said, this most likely would be primitives from the Xilinx unisim library.
The best option is to probably run the EDIF files you have through the Xilinx tools (specifically "Translate" (ngdbuild) and "Generate Simulation Netlist" (netgen)) to generate a simulation model for these pieces. The result will likely require the Xilinx unisim and simprims libraries, which are usually available precompiled for most simulators, but can also easily just be pointed to the source in the Xilinx ISE install.
I'm using VHDL on Xilinx ISE to generate a schematic of the register transfer logic in my project. I know ISE does a number of optimizations and gate reductions before spitting out the RTL and Technology schematics. What I want to do is to export the netlist of these schematics into some file so I can use that for my own program. Is there any way to do this? I keep reading about ngc files, but the contents of the ngc file generated upon synthesis make absolutely no sense.
Please let me know if you've done this before, I'd love to see how this is done. If it's not doable on ISE, can you recommend a tool that could do it?
EDIF is an industry standard format for describing netlists - there are numerous tools for interpreting them and you could easily roll your own since it's a documented textual format.
You can convert an .ngc into an edif file by running the Xilinx tool ngc2edif included in the ISE suite.
Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!
Active HDL has a feature called "Code2Graphics" which supports this.
Additionally, some synthesis tools (typically ones you would have to pay for) also support this.
Note that an RTL view is more commonly available in synthesis tools (such as XST).
Modelsim SE (and DE?) have these kind of things. But, not for free :-(