Is it possible to get the same output of make --debug=basic
without the compiling commands to be executed?
I would like to get the same behaviour of a make --just-print
but with make --debug=basic's output.
From #Beta's comment: make --debug=basic --just-print does the job.
Related
I want to add a new fortran module into an existing fortran90 program. The existing fortran90 program is compiled by firstly running ./configure, then run the make and make install. If I want to define my own innovation, what else I need to do is export VER_USER=xxx, then make user and make installuser. It seems that make does the compilation job and make install does the installation job. And I need to add something like gfortran -o using_FKB using_FKB.o other.o ... -L/path_of_lib -lnewlib or path/to/libneural.a. So I need to debug the original Makefile. But I found it's difficult because the original Makefile is too long. I tried to use make -V=1 or make -d, and also make SHELL='sh -x' , but they prints so much things on my terminal...I could hardly debug. Is there anyway to debug it step by step?
By the way, there are too much $() variable in the Makefile. When I use ``make -V=1ormake -d, and also make SHELL='sh -x' , I found they hardly print the command in Makefilelike$(OBJ_PATH)=/path/obj_path...and it's quite hard for me to debug this...so is there any way to debug the Makefile``` step by step? Thanks!
GNU make version 3.81, when I tab make -j20, there are so many errors and warnings. But when tab "make", then it will seccess ? Is there any relation with include "../build/Generic.mak"?
or when make -j20 will failed?
Sounds like your Makefile is simply not thread safe. That's why it doesn't work with -j parameter. The -j option tells make to run in parallel.
Unfortunately, the Makefile language is too complex to know exactly what is wrong with your build with the information you've given. It's a rather involved subject but you could try to read (a lot) about GNU make and automake to find some insight.
I'm building a Makefile for a sequence of compiles to show progressive output differences to be used to synchronize with the examples in a tutorial. Some of those runs generates error codes, but since that is part of the definition of the "problem" the message output by make ("Makefile:15: recipe for target `run3' failed") when a target fails kind of gets in the way.
I know about ignoring the error code, but is it possible to suppress that output? Preferable from within the Makefile.
On a similar note, is it possible to suppress the message of entering and leaving subdirectories from within the Makefile (equivalent to '--no-print-directory')?
And, yes, I'm satisfied with a GNU Make answer.
Of course, after some googling the answer is in the GNU Make manual. The special targets .SILENT and .IGNORE did exactly what I wanted.
To achieve what you want I would use --silent --ignore-errors --no-print-directory GNU make switches and redirect stderr to /dev/null (2>/dev/null) commands in the makefile
I am absolutely new in gfortran+minGW.
I need to create makefile.
When I run
$ gfortran -c q.f
All is ok!
But how can I run makefile like this?
CC = gfortran
q.o : q.f
$(CC) -c q2.o q2.f
I receive error “CC: command not found”.
(OS – Win 7 (64))
Tanks!!!
It kind of looks like you're trying to run the makefile as a regular script. Try
$ make
or
$ make -f mymakefilename
if you named the file something other than "makefile" or "Makefile".
You can potentially just execute the makefile, but if so you need a "shebang" line, something like
#!/usr/bin/make
at the top of the file, but frankly hardly anyone uses that option. Just use the make(1) command.
Update
It's because they're in the wrong order. Makefiles process (by default) the first target in the file. When you run make it sees the rule to make, q.o from q.f, it compiles it, and says, "Okay, I'm done."
If you put the q.exe target first, it says "Hmmm, I want to build q.exe and to do that I need a q.o. Do I have a q.o? No? Okay, hen I'll build a q.o. I have a rule for that -- I can build a q.o from q.f. okay, that's done. Now can I build q.exe? Oh, yes, I can. I'll build q.exe. Anything? Nope, I'm done."
If you were to use the commend
$ make q.exe
then you'd explicitly tell make to make q.exe, which would cause the same thing to happen, but better you should reorder your makefile and get used to the way they work.
Is there a way to have make echo commands that are manually suppressed with # in the makefile? I can't find this in the help or man page, it just says "--quiet" to do the opposite.
The most obvious idea is to change the shell that runs the commands, e.g. modify your makefile and add to the top SHELL = sh -xv.
Another solution is to change how you call make to make SHELL='sh -xv'
Lastly if your Makefile is generated by cmake then call make with make VERBOSE=1
I run into this question from time to time using cmake because it hides the command. You can use "make VERBOSE=true" to get them to print out.