what do $(MAKE) and $(MAKEFILES) do
some tutorials say that we'd better not use the variable MAKEFILES, and i dont know why.
hope someone can explain, thx.
Related
I mean, there is sample code like:
runner.OnDiscoveryComplete = OnDiscoveryComplete;
But what does it mean? When does "OnDiscoveryComplete" happen? Also, I am not clear on the implementation. Do you simply set up all parts and then call instanceOfAssemblyTestRunner.Start()? Also in the past I used my Tests with "Dotnet test" from the shell. I guess now I have to compile and execute?
Any help is greatly appreciated.
We have unit tests in our project, and they run very slowly. The main reason for this, as far as I can tell is that each subdir runs serially. There is no reason for this and I'd like to modify things so each subdirectory is processed in parallel.
I found this question but it seems that the accepted answer is for how to specify this in your makefile, and not the makefile.am. I tried just adding the solution to my Makefile.am and it didn't seem to make a difference. Is this the correct way to do it at a Makefile.am level? If so, any advice for what I could be doing wrong? If not, please show me the path of truth :-)
In answer to my question, things from Makefile.am are translated fairly directly to the Makefile, so the changes in the original question can be made in Makefile.am. The only part I'm not 100% confident on is whether or not SUBDIRS (as it has special meaning) can get mangled in the autotools process. At any rate, processing the SUBDIRS in parallel is perhaps not typically the answer.
I solved this was to use a separate target for the directories I wanted processed in parallel, and I bet that this is typically the correct answer. There may well be some way to get the SUBDIRs to be processed this way, but using a separate target was pretty easy to get working for me, and at least for what I was trying to do a separate target was more appropriate.
I still don't understand why "phony" rules in Makefiles have ".PHONY" as their target. It would be much more logical as a prerequisite.
Do I have to elaborate on this? If A depends on B and B is phony, then A is phony too. So the dependency graph .PHONY←B→A is waay surprising compared to .PHONY→B→A. (Another argument is that an implementation of make must handle the .PHONY target very special.)
While this critique may seem rather theoretical (to pointless) - "since make is so ancient, its syntax is here to stay". But I am not proposing any syntax change, there is an alternative:
With GNU Make (at least), the following Makefile declares a phony target_A:
target_A: _PHONY
touch target_A
_PHONY:
#noop
Question 1: This is so simple and clean, surely I am not its first inventor. In fact, given this alternative, why did make ever need the special syntax?
It seems to me that this would also quite nicely solve questions about wildcards in phony targets, and could even shed some light on .PHONY's meaning when beginners doubt.
Question 2: Can you think of any circumstance where this approach is inferior? (Is invoking make .PHONY of any use?)
(I should mention that while I have invoked other makes, GNU Make is the only implementation that I have some experience with - reading and writing Makefiles.)
One big problem with using target_A: .PHONY is that it makes it much harder to use many of make's built-in variables. Take this common recipe as an example:
%.a: $(OBJ_FILES)
$(LD) $(LFLAGS) -o $# $^
The $^ variable pulls in everything that's listed as a prerequisite. If .PHONY was also listed there then it would be passed to the linker on the command-line, which would probably not result in anything good happening. Using meta-targets like .PHONY as prerequisites makes these built-in variables significantly less useful, as they require a lot of extra processing like $(filter-out .PHONY,$^) every time they are used. Inverting the relationship and instead making .PHONY the target is a bit awkward for the sake of thinking about dependency trees, but it cleans up the rest of the makefile.
here I am again with another make issue Im trying to handle (hardly), I have set several values I want make to read, but when I try to change inside a loop it does not work; $(FOUND) stills being the same as it was first, what could I being doing bad? is other way to set variables or to change them into?
here's a part of my code related to this question:
$(shell for d in $(INPUT); \
do \
$(if $(FOUND) -eq 1, REL=$(REL)../); \
$(if $(findstring $(WORD),$(INPUT)), \
echo '$(WORD)../'; FOUND=1)\
done)
$(FOUND) variable is defined outside but want it to change when it gets $(WORD)
any suggestion for that???
thank you so much
There are several things wrong with the code above, so much so that it is difficult to understand your intention. Here is a partial list (sorry if I sound like Microsoft clippy)
The code $(if $(FOUND) -eq 1, REL=$(REL)../), looks like a mix between gnu-make syntax and shell syntax.
Your loop seems to be superfluous. You are not using the loop variable d, and you are using a construct that process the entire sequence. E.g.: $(findstring $(WORD),$(INPUT)
It seems that you are trying to generate code like echo '$(WORD)../', but the context of this code is unclear. If it is outside a rule, the code has no meaning. If it is inside a rule, it will evaluate too late to set a makefile variable. There is a way to work around this problem, but first you need to clarify your intention better.
I can only suspect you intended to have REL=$(REL)/.. or REL=../$(REL) but I can be mistaken.
Lastly it is important to understand that what you really should do in a Makefile is to describe a dependency graph, and let make figure out the order of operation needed to be performed. So a procedural approach such as may inferred from your code above should be minimized.
Edit:
If I read you correctly, you are trying to achieve a tricky goal in Makefile. Let me assure you that your inexperience is not the only stumbling block you have. Writing good Makefiles is hard. If you have any control over this, I strongly suggest to have a look at some other build solutions. For example, cmake can write good Makefiles for you.
If you are trying to calculate a base-dir or a relative-dir, please note that the concept of current-working-directory as saved in $(CURDIR) might or might not be what you expect.
For your question, you can indeed use a GNU make $(foreach ...) construct, but there are several functions that are designed to handle sequences without iterations, that might serve you better.
I'm no Makefile expert, and I was wondering if someone knew of some kind of analyzer or simulator that would start from the top-most Makefile all the way down to the inner-most Makefile, each time showing me the value of each variable and the order in which it goes through rules.
Thank you.
Most implementations of make offer the -d flag which will cause the program to print out everything it is doing, in great detail. The -n flag will cause make to do a dry-run, ie report what it would do but not actually do it.
Be warned, make produces a lot of output so you probably want to redirect it to a file for your later perusal.